74VHC139 Dual 2-to-4 Decoder/Demultiplexer
November 1992
Revised April 1999
74VHC139
Dual 2-to-4 Decoder/Demultiplexer
General Description
The VHC139 is an advanced high speed CMOS Dual 2-to-
4 Decoder/Demultiplexer fabricated with silicon gate
CMOS technology. It achieves the high speed operation
similar to equivalent Bipolar Schottky TTL while maintain-
ing the CMOS low power dissipation.
The active LOW enable input can be used for gating or it
can be used as a data input for demultiplexing applications.
When the enable input is held HIGH, all four outputs are
fixed at a HIGH logic level independent of the other inputs.
An input protection circuit ensures that 0V to 7V can be
applied to the input pins without regard to the supply volt-
age. This device can be used to interface 5V to 3V systems
and two supply systems such as battery back up. This cir-
cuit prevents device destruction due to mismatched supply
and input voltages.
Features
s
High Speed: t
PD
=
5.0 ns (typ) at T
A
=
25°C
s
Low power dissipation: I
CC
=
4
µA
(Max.) at T
A
=
25°C
s
High noise immunity: V
NIH
=
V
NIL
=
28% V
CC
(Min.)
s
Power down protection is provided on all inputs
s
Pin and function compatible with 74HC139
Ordering Code:
Order Number
74VHC139M
74VHC139SJ
74VHC139MTC
74VHC139N
Package Number
M16A
M16D
MTC16
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Description
Pin Names
A
0
, A
1
E
O
0
–O
3
Description
Address Inputs
Enable Inputs
Outputs
Truth Table
Inputs
E
H
L
L
L
L
A
0
X
L
H
L
H
A
1
X
L
L
H
H
O
0
H
L
H
H
H
Outputs
O
1
H
H
L
H
H
O
2
H
H
H
L
H
O
3
H
H
H
H
L
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
© 1999 Fairchild Semiconductor Corporation
DS011521.prf
www.fairchildsemi.com
74VHC139
Logic Symbols
Functional Description
The VHC139 is a high-speed dual 2-to-4 decoder/demulti-
plexer. The device has two independent decoders, each of
which accepts two binary weighted inputs (A
0
–A
1
) and pro-
vides four mutually exclusive active-LOW outputs (O
0
–O
3
).
Each decoder has an active-LOW enable (E). When E is
HIGH all outputs are forced HIGH. The enable can be used
as the data input for a 4-output demultiplexer application.
Each half of the VHC139 generates all four minterms of
two variables. These four minterms are useful in some
applications, replacing multiple gate functions as shown in
Figure 1
, and thereby reducing the number of packages
required in a logic network.
IEEE/IEC
FIGURE 1. Gate Functions (Each Half)
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.fairchildsemi.com
2
74VHC139
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
DC Input Voltage (V
IN
)
DC Output Voltage (V
OUT
)
Input Diode Current (I
IK
)
Output Diode Current (I
OK
)
DC Output Current (I
OUT
)
DC V
CC
/GND Current (I
CC
)
Storage Temperature (T
STG
)
Lead Temperature (T
L
)
(Soldering, 10 seconds)
260°C
−0.5V
to
+7.0V
−0.5V
to
+7.0V
−0.5V
to V
CC
+
0.5V
−20
mA
±20
mA
±25
mA
±75
mA
−65°C
to
+150°C
Recommended Operating
Conditions
(Note 2)
Supply Voltage (V
CC
)
Input Voltage (V
IN
)
Output Voltage (V
OUT
)
Operating Temperature (T
OPR
)
Input Rise and Fall Time (t
r
, t
f
)
V
CC
=
3.3V
±
0.3V
V
CC
=
5.0V
±
0.5V
0
∼
100 ns/V
0
∼
20 ns/V
2.0V to
+5.5V
0V to
+5.5V
0V to V
CC
−40°C
to
+85°C
Note 1:
Absolute Maximum Ratings are values beyond which the device
may be damaged or have its useful life impaired. The databook specifica-
tions should be met, without exception, to ensure that the system design is
reliable over its power supply, temperature, and output/input loading vari-
ables. Fairchild does not recommend operation outside databook specifica-
tions.
Note 2:
Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
OH
Parameter
HIGH Level
Input Voltage
LOW Level
Input Voltage
HIGH Level
Output Voltage
V
CC
(V)
2.0
3.0
−
5.5
2.0
3.0
−
5.5
2.0
3.0
4.5
3.0
4.5
V
OL
LOW Level
Output Voltage
2.0
3.0
4.5
3.0
4.5
I
IN
I
CC
Input Leakage Current
Quiescent Supply Current
0
−
5.5
5.5
1.9
2.9
4.4
2.58
3.94
0.0
0.0
0.0
0.1
0.1
0.1
0.36
0.36
±0.1
4.0
2.0
3.0
4.5
T
A
=
25°C
Min
1.50
0.7 V
CC
0.50
0.3 V
CC
1.9
2.9
4.4
2.48
3.80
0.1
0.1
0.1
0.44
0.44
±1.0
40.0
V
µA
µA
I
OL
=
4 mA
I
OL
=
8 mA
V
IN
=
5.5V or GND
V
IN
=
V
CC
or GND
V
V
I
OH
= −4
mA
I
OH
= −8
mA
V
IN
=
V
IH
I
OL
=
50
µA
or V
IL
V
Typ
Max
T
A
= −40°C
to
+85°C
Min
1.50
0.7 V
CC
0.50
0.3 V
CC
Max
Units
V
V
V
IN
=
V
IH
I
OH
= −50 µA
or V
IL
Conditions
AC Electrical Characteristics
Symbol
t
PLH
t
PHL
Parameter
Propagation Delay
A
n
to O
n
5.0
±
0.5
t
PLH
t
PHL
Propagation Delay
E
n
to O
n
5.0
±
0.5
C
IN
C
PD
Input Capacitance
Power Dissipation Capacitance
3.3
±
0.3
V
CC
(V)
3.3
±
0.3
T
A
=
25°C
Min
Typ
7.2
9.7
5.0
6.5
6.4
8.9
4.4
5.9
4
26
Max
11.0
14.5
7.2
9.2
9.2
12.7
6.3
8.3
10
T
A
= −40°C
to
+85°C
Min
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Max
13.0
16.5
8.5
10.5
11.0
14.5
7.5
9.5
10
Units
Conditions
C
L
=
15 pF
C
L
=
50 pF
C
L
=
15 pF
C
L
=
50 pF
C
L
=
15 pF
C
L
=
50 pF
C
L
=
15 pF
C
L
=
50 pF
V
CC
=
Open
(Note 3)
ns
ns
ns
ns
pF
pF
Note 3:
C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average
operating current can be obtained by the equation: I
CC
(opr.)
=
C
PD
* V
CC
* f
IN
+
I
CC
/2 (per decoder).
3
www.fairchildsemi.com
74VHC139
Physical Dimensions
inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
Package Number M16A
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
www.fairchildsemi.com
4
74VHC139
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC16
5
www.fairchildsemi.com
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
