FemtoClock
®
NG Crystal-to-LVCMOS/
LVTTL Clock Synthesizer
General Description
The ICS840N011I is an LVCMOS/LVTTL clock synthesizer designed
for Fibre Channel applications. The device generates a 106.25MHz
clock signal from a 26.5625MHz crystal or a 100MHz clock signal
from a 25MHz crystal with excellent phase jitter performance. The
device uses IDT’s fourth generation FemtoClock
®
NG technology for
an optimum of high clock frequency, low phase noise performance
and low power consumption and high power supply noise
rejection.The device supports 2.5V or 3.3V voltage supply and is
packaged in a small, lead-free (RoHS 6) 8-lead TSSOP package.
The extended temperature range supports wireless infrastructure,
telecommunication and networking end equipment requirements.
ICS840N011I
DATASHEET
Features
•
•
•
•
•
•
•
•
•
Fourth generation FemtoClock
®
NG technology
106.25MHz output clock synthesized from a 26.5625MHz
fundamental mode crystal
One 2.5V or 3.3V LVCMOS/LVTTL clock output
Crystal interface designed for a 12pF parallel resonant crystal
RMS phase jitter @ 100MHz, using a 25MHz crystal
(637kHz - 10MHz): 0.185ps (maximum)
LVCMOS/LVTTL interface level for the output enable input
Full 2.5V or 3.3V supply voltage
Lead-free (RoHS 6) packaging
-40°C to 85°C ambient operating temperature
Frequency Table
f
XTAL
(MHz)
25
26.5625
30.72
31.25
Output Frequency (MHz)
100
106.25
122.88
125
Function Table
Input
OE
0
1 (default)
Output Enable
Output Q is disabled in high-impedance state
Output Q is enabled.
NOTE: OE is an asynchronous control.
Block Diagram
XTAL_IN
OSC
XTAL_OUT
PFD
&
LPF
FemtoClock
®
NG
VCO
588-765MHz
÷6
Q
Pin Assignment
VDDA
OE
XTAL_OUT
XTAL_IN
1
2
3
8
7
6
5
VDD
Q
GND
DNU
4
÷24
OE
Pullup
ICS840N011I
8-lead TSSOP
4.40mm x 3.0mm x 0.925mm
package body
G Package
Top View
ICS840N011BGI REVISION A AUGUST 16, 2013
1
©2013 Integrated Device Technology, Inc.
ICS840N011I Data Sheet
FEMTOCLOCK
®
NG CRYSTAL-TO-LVCMOS/LVTTL CLOCK SYNTHESIZER
Pin Descriptions and Characteristics
Table 1. Pin Descriptions
Number
1
2
3,
4
5
6
7
8
Name
V
DDA
OE
XTAL_OUT,
XTAL_IN
DNU
GND
Q
V
DD
Power
Output
Power
Power
Input
Input
Pullup
Type
Description
Analog power supply.
Output enable pin. LVCMOS interface levels.
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
Do not use. Do not connect.
Power supply ground.
Single-ended clock output. LVCMOS/LVTTL interface levels.
Core supply pin.
NOTE:
Pullup
refers to an internal input resistor. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
C
PD
R
PULLUP
R
OUT
Parameter
Input Capacitance
Power Dissipation
Capacitance
Input Pullup Resistor
Output Impedance
V
DD
= 3.3V
V
DD
=2.5V
Test Conditions
OE
V
DD
= 3.465V
V
DD
= 2.625V
Minimum
Typical
3.5
11
9
51
15
19
Maximum
Units
pF
pF
pF
k
ICS840N011BGI REVISION A AUGUST 16, 2013
2
©2013 Integrated Device Technology, Inc.
ICS840N011I Data Sheet
FEMTOCLOCK
®
NG CRYSTAL-TO-LVCMOS/LVTTL CLOCK SYNTHESIZER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics or AC
Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
XTAL_IN
Other Inputs
Outputs, V
O
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
3.63V
0V to 2V
-0.5V to V
DD
+ 0.5V
-0.5V to V
DD
+ 0.5V
117°C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 3A. Power Supply DC Characteristics, V
DD
= 3.3V±5% or 2.5V±5%, T
A
= -40°C to 85°C
Symbol
V
DD
V
DDA
V
DDA
I
DDA
I
DD
Parameter
Core Supply Voltage
Analog Supply Voltage
Analog Supply Voltage
Analog Supply Current
Power Supply Current
Test Conditions
Minimum
2.375
V
DD
– 0.18
V
DD
– 0.18
Typical
3.3
3.3
2.5
Maximum
3.465
V
DD
V
DD
18
67
Units
V
V
V
mA
mA
Table 3B. LVCMOS/LVTTL DC Characteristics,
V
DD
= 3.3V±5% or 2.5V±5%, T
A
= -40°C to 85°C
Symbol
V
IH
Parameter
Input High Voltage
Test Conditions
V
DD
= 3.3V
V
DD
= 2.5V
Input Low Voltage
Input High Current
Input Low Current
Output High
Voltage;
NOTE 1
Output Low Voltage;
NOTE 1
OE
OE
V
DD
= 3.3V
V
DD
= 2.5V
V
DD
= V
IN
= 3.465V or 2.625V
V
DD
= 3.465V 3.465V or 2.625V,
V
IN
= 0V
V
DD
= 3.465V
Q
V
DD
= 2.625V
Q
V
DD
= 3.465V or 2.625V
1.8
0.5
V
V
-150
2.6
Minimum
2
1.7
-0.3
-0.3
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
0.7
5
Units
V
V
V
V
µA
µA
V
V
IL
I
IH
I
IL
V
OH
V
OL
NOTE 1: Output terminated with 50 to V
DD
/ 2. See Parameter Measurement Information Section,
LVCMOS Output Load Test Circuit Diagrams.
ICS840N011BGI REVISION A AUGUST 16, 2013
3
©2013 Integrated Device Technology, Inc.
ICS840N011I Data Sheet
FEMTOCLOCK
®
NG CRYSTAL-TO-LVCMOS/LVTTL CLOCK SYNTHESIZER
Table 4. Crystal Characteristics
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Capacitive Load (C
L
)
12
24.50
Test Conditions
Minimum
Typical
Fundamental
26.5625
31.88
80
7
MHz
pF
pF
Maximum
Units
AC Characteristics
Table 5. AC Characteristics,
V
DD
= 3.3V±5% or 2.5V±5%, T
A
= -40°C to 85°C
Symbol
f
OUT
Parameter
Output Frequency
f
OUT
= 100MHz, 25MHz Crystal,
Integration Range: 637kHz –
10MHz
f
OUT
= 106.25MHz, 26.5625MHz
Crystal, Integration Range:
637kHz – 10MHz
f
OUT
= 106.25MHz, Offset: 10Hz
f
OUT
= 106.25MHz, Offset: 100Hz
f
OUT
= 106.25MHz, Offset: 1kHz
N
Single-Side Band Noise
Power
f
OUT
= 106.25MHz, Offset: 10kHz
f
OUT
= 106.25MHz,
Offset: 100kHz
f
OUT
= 106.25MHz, Offset: 1MHz
f
OUT
= 106.25MHz, Offset: 10MHz
t
R
/ t
F
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
200
48
Test Conditions
Minimum
98.00
Typical
106.25
0.140
Maximum
127.52
0.185
Units
MHz
ps
tjit(Ø)
RMS Phase Jitter
(Random);
NOTE 1
0.139
-60.4
-87.4
-117.8
-130.7
-134.9
-145.6
-158.9
0.177
ps
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
600
52
ps
%
NOTE: Characterized with 25MHz, 26.5625MHz, 30.72MHz and 31.25MHz crystals.
NOTE 1: Please refer to the phase noise plots.
ICS840N011BGI REVISION A AUGUST 16, 2013
4
©2013 Integrated Device Technology, Inc.
ICS840N011I Data Sheet
FEMTOCLOCK
®
NG CRYSTAL-TO-LVCMOS/LVTTL CLOCK SYNTHESIZER
Typical Phase Noise at 100MHz (637kHz - 10MHz)
Noise Power (dBc/Hz)
Offset Frequency (Hz)
Typical Phase Noise at 106.25MHz (637kHz - 10MHz)
Noise Power (dBc/Hz)
Offset Frequency (Hz)
ICS840N011BGI REVISION A AUGUST 16, 2013
5
©2013 Integrated Device Technology, Inc.
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