74ABT74
Dual D-type flip-flop with set and reset; positive edge-trigger
Rev. 2 — 12 August 2016
Product data sheet
1. General description
The 74ABT74 high-performance BiCMOS device combines low static and dynamic power
dissipation with high speed and high output drive.
The 74ABT74 is a dual positive edge-triggered D-type flip-flop featuring individual data,
clock, set, and reset inputs; also true and complementary outputs. Set (nSD) and reset
(nRD) are asynchronous active low inputs and operate independently of the clock input.
When set and reset are inactive (HIGH), data at the nD input is transferred to the nQ and
nQ outputs on the LOW-to-HIGH clock transition. Data must be stable just one setup time
prior to the LOW-to-HIGH clock transition for predictable operation. Clock triggering
occurs at a voltage level and is not directly related to the transition time of the
positive-going pulse. Following the hold time interval, data at the nD input may be
changed without affecting the levels of the output.
2. Features and benefits
Latch-up protection exceeds 500 mA per JESD78B class II level A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from
40 C
to +85
C
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74ABT74D
74ABT74DB
74ABT74PW
40 C
to +85
C
40 C
to +85
C
40 C
to +85
C
SO14
SSOP14
TSSOP14
Description
plastic small outline package; 14 leads;
body width 3.9 mm
plastic shrink small outline package; 14 leads;
body width 5.3 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
Version
SOT108-1
SOT337-1
SOT402-1
Type number
Nexperia
74ABT74
Dual D-type flip-flop with set and reset; positive edge-trigger
4. Functional diagram
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
Fig 3.
Logic diagram for one flip-flop
5. Pinning information
5.1 Pinning
Fig 4.
74ABT74
Pin configuration for SO14
Fig 5.
Pin configuration for SSOP14 and TSSOP14
©
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 2 — 12 August 2016
2 of 15
Nexperia
74ABT74
Dual D-type flip-flop with set and reset; positive edge-trigger
5.2 Pin description
Table 2.
Symbol
1RD, 2RD
1D, 2D
1CP, 2CP
1SD, 2SD
1Q, 2Q
1Q, 2Q
GND
V
CC
Pin description
Pin
1, 13
2, 12
3, 11
4, 10
5, 9
6, 8
7
14
Description
asynchronous reset-direct input (active LOW)
data input
clock input (LOW-to-HIGH, edge-triggered)
asynchronous set-direct input (active LOW)
output
complement output
ground (0 V)
supply voltage
6. Functional description
Table 3.
Input
nSD
L
H
L
H
H
[1]
Function table
[1]
Output
nRD
H
L
L
H
H
nCP
X
X
X
nD
X
X
X
h
l
nQ
H
L
H
H
L
nQ
L
H
H
L
H
Asynchronous set
Asynchronous reset
Undetermined
[2]
Load “1”
Load “0”
Operating mode
H = HIGH voltage level
h = HIGH voltage level one setup time prior to low-to-high clock transition
L = LOW voltage level
l = LOW voltage level one setup time prior to low-to-high clock transition
X = don’t care
= LOW-to-HIGH clock transition
[2]
This setup is unstable and changes when either set or reset returns to the high level.
74ABT74
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 2 — 12 August 2016
3 of 15
Nexperia
74ABT74
Dual D-type flip-flop with set and reset; positive edge-trigger
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
T
j
T
stg
[1]
[2]
Parameter
supply voltage
input voltage
output voltage
input clamping current
output clamping current
output current
junction temperature
storage temperature
Conditions
[1]
Min
0.5
1.2
0.5
18
50
-
[2]
Max
+7.0
+7.0
+5.5
-
-
40
150
+150
Unit
V
V
V
mA
mA
mA
C
C
output in OFF-state or HIGH-state
V
I
< 0 V
V
O
< 0 V
output in LOW-state
[1]
-
65
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150
C.
8. Recommended operating conditions
Table 5.
Operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
V
IH
V
IL
I
OH
I
OL
t/V
T
amb
Parameter
supply voltage
input voltage
HIGH-level input voltage
LOW-level input voltage
HIGH-level output current
LOW-level output current
input transition rise and fall rate
ambient temperature
in free air
Conditions
Min
4.5
0
2.0
-
15
-
0
40
Typ
-
-
-
-
-
-
-
-
Max
5.5
V
CC
-
0.8
-
20
10
+85
Unit
V
V
V
V
mA
mA
ns/V
C
74ABT74
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 2 — 12 August 2016
4 of 15
Nexperia
74ABT74
Dual D-type flip-flop with set and reset; positive edge-trigger
9. Static characteristics
Table 6.
Symbol
V
IK
V
OH
V
OL
I
I
I
OFF
I
CEX
I
O
I
CC
I
CC
Static characteristics
Parameter
Conditions
Min
input clamping voltage V
CC
= 4.5 V; I
IK
=
18
mA
HIGH-level output
voltage
LOW-level output
voltage
input leakage current
power-off leakage
current
output high leakage
current
output current
supply current
additional supply
current
input capacitance
V
CC
= 4.5 V; I
OH
=
15
mA;
V
I
= V
IL
or V
IH
V
CC
= 4.5 V; I
OL
= 20 mA;
V
I
= V
IL
or V
IH
V
CC
= 5.5 V; V
I
= GND or 5.5 V
V
CC
= 0 V; V
I
or V
O
4.5 V
HIGH-state; V
O
= 5.5 V;
V
CC
= 5.5 V; V
I
= GND or V
CC
V
CC
= 5.5 V; V
O
= 2.5 V
V
CC
= 5.5 V; V
I
= GND or V
CC
per input pin; V
CC
= 5.5 V;
one input at 3.4 V;
other inputs at V
CC
or GND
V
I
= 0 V or V
CC
[2]
[1]
25
C
Typ
0.9
2.9
0.35
Max
-
-
0.5
1.2
2.5
-
-
-
-
50
-
-
40 C
to +85
C
Unit
Min
1.2
2.5
-
-
-
-
50
-
-
Max
-
-
0.5
1.0
100
50
180
50
500
V
V
V
A
A
A
mA
A
A
0.01 1.0
5.0
5.0
75
2
0.25
100
50
180
50
500
C
I
[1]
[2]
-
3
-
-
-
pF
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
This is the increase in supply current for each input at 3.4 V.
10. Dynamic characteristics
Table 7.
Dynamic characteristics
GND = 0 V; for test circuit, see
Figure 9.
Symbol Parameter
Conditions
25
C;
V
CC
= 5.0 V
Min
f
max
t
PLH
t
PHL
t
PLH
t
PHL
t
sk(o)
maximum
frequency
LOW to HIGH
propagation delay
HIGH to LOW
propagation delay
LOW to HIGH
propagation delay
HIGH to LOW
propagation delay
output skew time
nCP; see
Figure 6
nCP to nQ, nQ; see
Figure 6
nCP to nQ, nQ; see
Figure 6
nSD, nRD to nQ, nQ; see
Figure 7
nSD, nRD to nQ, nQ; see
Figure 7
[1]
40 C
to +85
C;
Unit
V
CC
= 5.0 V
0.5 V
Min
150
1.0
1.0
1.0
1.0
-
Max
-
4.7
4.0
6.2
5.2
0.6
MHz
ns
ns
ns
ns
ns
Typ
250
3.0
2.5
3.4
2.9
0.5
Max
-
4.2
3.5
4.9
4.5
0.6
180
1.0
1.0
1.0
1.0
-
74ABT74
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 2 — 12 August 2016
5 of 15
嵌入式系统
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