June 1997
NDS332P
P-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
These P-Channel logic level enhancement mode power field
effect transistors are produced using Fairchild's proprietary, high
cell density, DMOS technology. This very high density process is
especially tailored to minimize on-state resistance. These
devices are particularly suited for low voltage applications such as
notebook computer power management, portable electronics,
and other battery powered circuits where fast high-side
switching, and low in-line power loss are needed in a very small
outline surface mount package.
Features
-1 A, -20 V, R
DS(ON)
= 0.41
Ω
@ V
GS
= -2.7 V
R
DS(ON)
= 0.3
Ω
@ V
GS
= -4.5 V.
Very low level gate drive requirements allowing direct
operation in 3V circuits. V
GS(th)
< 1.0V.
Proprietary package design using copper lead frame for
superior thermal and electrical capabilities.
High density cell design for extremely low R
DS(ON)
.
Exceptional on-resistance and maximum DC current
capability.
Compact industry standard SOT-23 surface Mount
package.
________________________________________________________________________________
D
G
S
A solute Maximum Ratings
Symbol
V
DSS
V
GSS
I
D
P
D
T
J
,T
STG
Parameter
Drain-Source Voltage
T
A
= 25°C unless otherwise noted
NDS332P
-20
±8
(Note 1a)
Units
V
V
A
Gate-Source Voltage - Continuous
Drain Current - Continuous
- Pulsed
Maximum Power Dissipation
(Note 1a)
(Note 1b)
-1
-10
0.5
0.46
-55 to 150
W
Operating and Storage Temperature Range
°C
THERMAL CHARACTERISTICS
R
θ
JA
R
θ
JC
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
250
75
°C/W
°C/W
© 1997 Fairchild Semiconductor Corporation
NDS332P Rev. E
Electrical Characteristics
(T
A
= 25°C unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
OFF CHARACTERISTICS
BV
DSS
I
DSS
Drain-Source Breakdown Voltage
Zero Gate Voltage Drain Current
V
GS
= 0 V, I
D
= -250 µA
V
DS
= -16 V, V
GS
= 0 V
T
J
= 55°C
I
GSS
I
GSS
Gate - Body Leakage
Current
Gate - Body Leakage
Current
V
GS
= 8 V, V
DS
= 0 V
V
GS
= -8 V, V
DS
= 0 V
-20
-1
-10
100
-100
V
µA
µA
nA
nA
ON CHARACTERISTICS
(Note 2)
V
GS(th)
Gate Threshold Voltage
V
DS
= V
GS
, I
D
= -250 µA
T
J
=125°C
R
DS(ON)
Static Drain-Source On-Resistance
V
GS
= -2.7 V, I
D
= -1 A
T
J
=125°C
V
GS
= -4.5 V, I
D
= -1.1 A
I
D(ON)
On-State Drain Current
V
GS
= -2.7 V, V
DS
= -5 V
V
GS
= -4.5 V, V
DS
= -5 V
g
F
S
C
iss
C
oss
C
rss
t
D(on)
t
r
t
D(off)
t
f
Q
g
Q
gs
Q
gd
-1.5
-2.5
2.2
-0.4
-0.3
-0.6
-0.45
0.35
0.5
0.26
-1
-0.8
0.41
0.74
0.3
A
V
Ω
Forward Transconductance
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
V
DS
= -5 V, I
D
= -1 A
V
DS
= -10 V, V
GS
= 0 V,
f = 1.0 MHz
S
pF
pF
pF
DYNAMIC CHARACTERISTICS
195
105
40
SWITCHING CHARACTERISTICS
(Note 2)
Turn - On Delay Time
Turn - On Rise Time
Turn - Off Delay Time
Turn - Off Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
V
DS
= -5 V, I
D
= -1 A,
V
GS
= -4.5 V
V
DD
= -6 V, I
D
= -1 A,
V
GS
= -4.5 V, R
GEN
= 6
Ω
8
30
25
27
3.7
0.5
0.9
15
45
45
45
5
ns
ns
ns
ns
nC
nC
nC
NDS332P Rev. E
Electrical Characteristics
(T
A
= 25°C unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
V
SD
Maximum Continuous Source Current
Drain-Source Diode Forward Voltage
V
GS
= 0 V, I
S
= -0.42 A
(Note 2)
-0.75
-0.42
-1.2
A
V
Notes:
1. R
θ
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
θ
JC
is guaranteed by
design while R
θ
CA
is determined by the user's board design.
P
D
(t) =
T
J
−T
A
R
θJA
(t)
=
T
J
−T
A
R
θJC
+R
θCA
(t)
=
I
2
(t) ×
R
DS(ON)@T
J
D
Typical R
θ
JA
using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
a. 250
o
C/W when mounted on a 0.02 in
2
pad of 2oz copper.
b. 270
o
C/W when mounted on a 0.001 in
2
pad of 2oz copper.
1a
1b
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
NDS332P Rev. E
Typical Electrical Characteristics
-2.5
I
D
, DRAIN-SOURCE CURRENT (A)
1.8
-2.0
R
DS(ON)
, NORMALIZED
-2
-3.5
-3.0
DRAIN-SOURCE ON-RESISTANCE
V
GS
= -4.5V
-2.5
-2.7
1.6
1.4
V
GS
=-2.0V
1.2
-1.5
-2.5
1
0.8
0.6
0.4
-2.7
-3.0
-3.5
-4.5
-1
-1.5
-0.5
0
0
-0.5
V
DS
-1
-1.5
-2
-2.5
, DRAIN-SOURCE VOLTAGE (V)
-3
0
-0.5
-1
-1.5
-2
I , DRAIN CURRENT (A)
D
-2.5
-3
Figure 1. On-Region Characteristics
.
Figure 2. On-Resistance Variation
with Drain Current and Gate Voltage
.
1.8
DRAIN-SOURCE ON-RESISTANCE
DRAIN-SOURCE ON-RESISTANCE
1.6
1.4
1.2
1
0.8
0.6
0.4
-50
1.8
R
DS(ON)
, NORMALIZED
I
D
= -1A
V
GS
= -2.7
R
DS(on)
, NORMALIZED
V
GS
= -2.7 V
1.6
1.4
1.2
1
0.8
0.6
0.4
TJ = 125°C
25°C
-55°C
-25
0
25
50
75
100
T , JUNCTION TEMPERATURE (°C)
J
125
150
0
-0.5
-1
-1.5
-2
I , DRAIN CURRENT (A)
D
-2.5
-3
Figure 3. On-Resistance Variation
with Temperature
.
Figure 4. On-Resistance Variation
with Drain Current and Temperature
.
V
DS
= - 3V
-1.2
25°C
T = -55°C
J
125°C
V
th
, NORMALIZED
GATE-SOURCE THRESHOLD VOLTAGE (V)
-1.5
1.15
1.1
V
DS
= V
GS
I
D
= -250µA
I
D
, DRAIN CURRENT (A)
1.05
1
0.95
0.9
0.85
0.8
-50
-0.9
-0.6
-0.3
0
-0.5
-0.75
V
GS
-1
-1.25
-1.5
-1.75
-2
-25
, GATE TO SOURCE VOLTAGE (V)
0
25
50
75
100
T
J
, JUNCTION TEMPERATURE (°C)
125
150
Figure 5. Transfer Characteristics
.
Figure 6. Gate Threshold Variation
with Temperature.
NDS332P Rev.E
Typical Electrical Characteristics
(continued)
1.12
1
DRAIN-SOURCE BREAKDOWN VOLTAGE
V
GS
=0V
I
D
= -250µA
1.08
-I , REVERSE DRAIN CURRENT (A)
BV
DSS
, NORMALIZED
0.1
0.05
1.04
TJ = 125°C
0.01
25°C
-55°C
1
0.96
0.001
0.92
-50
-25
0
T
J
25
50
75
100
, JUNCTION TEMPERATURE (°C)
125
150
S
0.0001
0
0.2
0.4
0.6
0.8
-V
SD
, BODY DIODE FORWARD VOLTAGE (V)
1
Figure 7. Breakdown Voltage Variation with
Temperature
.
Figure 8. Body Diode ForwardVoltageVariation with
Source Current and Temperature
.
500
300
CAPACITANCE (pF)
200
5
-V
GS
, GATE-SOURCE VOLTAGE (V)
I
D
= -1A
V
DS
= -5V
-10V
-15V
4
Ciss
Coss
3
100
2
50
30
20
0.1
f = 1 MHz
V
GS
= 0V
0.2
-V
DS
Crss
1
0.5
1
2
5
, DRAIN TO SOURCE VOLTAGE (V)
10
20
0
0
1
2
3
Q
g
, GATE CHARGE (nC)
4
5
Figure 9. Capacitance Characteristics
.
Figure 10. Gate Charge Characteristics
.
V
DD
V
IN
D
t
on
t
d(on)
t
r
90%
t
off
t
d(off)
90%
t
f
R
L
V
OUT
DUT
V
GS
V
OUT
10%
10%
90%
R
GEN
G
V
IN
S
10%
50%
50%
PULSE WIDTH
INVERTED
Figure 11. Switching Test Circuit
.
Figure 12. Switching Waveforms
.
NDS332PRev. E
微控制器 MCU
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
