MR0A16A
FEATURES
•
•
•
•
•
•
•
•
•
3.3 Volt power supply
Fast 35ns read/write cycle
SRAM compatible timing
Unlimited read & write endurance
Commercial, Industrial, and Extended Temperatures
Data non-volatile for >20 years at temperature
RoHS-compliant TSOP2 and BGA packages available
All products meet MSL-3 moisture sensitivity level
Automotive AEC-Q100 Grade 1 option available
64K x 16 MRAM Memory
44-pin TSOP2
BENEFITS
• One memory replaces FLASH, SRAM, EEPROM and BBSRAM
in system for simpler, more efficient designs
• Improves reliability by replacing battery-backed SRAM
• Automatic data protection on power loss
48-ball BGA
RoHS
INTRODUCTION
The MR0A16A is a 1,048,576-bit magnetoresistive random access memory (MRAM) device organized as
65,536 words of 16 bits. The MR0A16A offers SRAM compatible 35 ns read/write timing with unlimited en-
durance. Data is always non-volatile for greater than 20 years. Data is automatically protected on power loss
by low-voltage inhibit circuitry to prevent writes with voltage out of specification.
MR0A16A is the ideal memory solution for applications that must permanently store and retrieve critical
data and programs quickly.
The MR0A16B is available in a small footprint 48-pin ball grid array (BGA) package and a 44-pin thin small
outline package (TSOP Type 2). These packages are compatible with similar low-power SRAM products and
other nonvolatile RAM products.
The MR0A16A provides highly reliable data storage over a wide range of temperatures. The product is avail-
able with commercial temperature (0 to +70 °C), industrial temperature (-40 to +85 °C), extended tempera-
ture (-40 to +105 °C), and Automotive AEC-Q100 Grade 1 (-40 to +125°) temperature range options.
Copyright © 2015 Everspin Technologies
1
MR0A16A Rev. 8.2, 6/2015
MR0A16A
TABLE OF CONTENTS
FEATURES .............................................................................................................................................1
BENEFITS...............................................................................................................................................1
INTRODUCTION ...................................................................................................................................1
BLOCK DIAGRAM AND PIN ASSIGNMENTS .......................................................................................4
Figure 1 – Block Diagram ........................................................................................................................................... 4
Table 1 – Pin Functions ............................................................................................................................................... 4
Figure 2 – MR0A16A Package Pinouts .................................................................................................................. 5
OPERATING MODES .............................................................................................................................5
Table 2 – Operating Modes ....................................................................................................................................... 5
ABSOLUTE MAXIMUM RATINGS .........................................................................................................6
Table 3 – Absolute Maximum Ratings ................................................................................................................... 6
OPERATING CONDITIONS ...................................................................................................................7
Table 4 – Operating Conditions ............................................................................................................................... 7
Power Up and Power Down Sequencing .......................................................................................8
Figure 3 – Power Up and Power Down Timing ................................................................................................. 8
DC CHARACTERISTICS .........................................................................................................................9
Table 5 – DC Characteristics ......................................................................................................................................
9
Table 6 – Power Supply Characteristics ................................................................................................................
9
TIMING SPECIFICATIONS ................................................................................................................. 10
Table 7 – Capacitance ...............................................................................................................................................10
Table 8 – AC Measurement Conditions ..............................................................................................................10
Figure 4 – Output Load Test Low and High .......................................................................................................10
Figure 5 – Output Load Test All Others ...............................................................................................................10
Table 9 – Read Cycle Timing ...................................................................................................................................11
Figure 6 – Read Cycle 1 .............................................................................................................................................12
Copyright © 2015 Everspin Technologies
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MR0A16A Rev. 8.2, 6/2015
MR0A16A
TABLE OF CONTENTS - continued
Figure 7 – Read Cycle 2 .............................................................................................................................................12
Table 10 – Write Cycle Timing 1 (W Controlled) .............................................................................................13
.
Figure 8 – Write Cycle Timing 1 (W Controlled) ...............................................................................................14
Table 11 – Write Cycle Timing 2 (E Controlled)................................................................................................15
Figure 9 – Write Cycle Timing 2 (E Controlled) ................................................................................................15
Table 12 – Write Cycle Timing 3 (LB/UB Controlled) ....................................................................................16
.
Figure 10 – Write Cycle Timing 3 (UB/LB Controlled) ...................................................................................16
ORDERING INFORMATION ............................................................................................................... 17
Table 13 – Part Numbering System ......................................................................................................................17
Table 14 – MR0A16A Ordering Part Numbers ..................................................................................................18
PACKAGE OUTLINE DRAWINGS ....................................................................................................... 19
Figure 11 – 44-pin TSOP2 .........................................................................................................................................19
Figure 12 – 48-ball FBGA ..........................................................................................................................................20
REVISION HISTORY ........................................................................................................................... 21
HOW TO CONTACT US ....................................................................................................................... 22
Copyright © 2015 Everspin Technologies
3
MR0A16A Rev. 8.2, 6/2015
MR0A16A
BLOCK DIAGRAM AND PIN ASSIGNMENTS
Figure 1 – Block Diagram
G
OUTPUT
ENABLE
BUFFER
8
8
ROW
DECODER
COLUMN
DECODER
SENSE
AMPS
8
UPPER BYTE OUTPUT ENABLE
LOWER BYTE OUTPUT ENABLE
UPPER
BYTE
OUTPUT
BUFFER
A[15:0]
16
ADDRESS
BUFFER
8
E
CHIP
ENABLE
BUFFER
16
64K x 16
BIT
MEMORY
ARRAY
16
8
LOWER
BYTE
OUTPUT
BUFFER
UPPER
BYTE
WRITE
DRIVER
8
W
WRITE
ENABLE
BUFFER
8
FINAL
WRITE
DRIVERS
8
8
DQU[15:8]
UB
LB
UB
BYTE
ENABLE
BUFFER
UPPER BYTE WRITE ENABLE
LOWER BYTE WRITE ENABLE
LOWER
BYTE
WRITE
DRIVER
8
DQL[7:0]
LB
Table 1 – Pin Functions
Signal Name
A
E
W
G
UB
LB
DQ
V
DD
V
SS
DC
NC
Function
Address Input
Chip Enable
Write Enable
Output Enable
Upper Byte Enable
Lower Byte Enable
Data I/O
Power Supply
Ground
Do Not Connect
No Connection
Copyright © 2015 Everspin Technologies
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MR0A16A Rev. 8.2, 6/2015
MR0A16A
Figure 2 – MR0A16A Package Pinouts
A
A
A
A
A
E
DQL0
DQL1
DQL2
DQL3
V
DD
V
SS
DQL4
DQL5
DQL6
DQL7
W
A
A
A
A
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A
A
A
G
UB
LB
DQU15
DQU14
DQU13
DQU12
V
SS
V
DD
DQU11
DQU10
DQU9
DQU8
DC
V
DD
V
SS
A
A
A
1
LB
DQU8
2
G
UB
DQU10
3
A0
A3
A5
A15
NC
A12
A10
A8
4
A1
A4
A6
V
SS
A14
A13
A11
A9
5
A2
E
DQL1
6
NC
DQL0
A
B
C
D
E
F
G
H
DQU9
DQL2
V
SS
V
DD
DQU14
DQU11
DQL3
V
DD
V
SS
DQL6
DQU12
DQL4
DQU13
DQL5
DQU15
NC
A7
W
V
DD
DQL7
NC
DC
44-Pin TSOP Type 2
48-Pin BGA
OPERATING MODES
Table 2 – Operating Modes
E
1
H
L
L
L
L
L
L
L
L
G
1
X
H
X
L
L
L
X
X
X
W
1
X
H
X
H
H
H
L
L
L
LB
1
X
X
H
L
H
L
L
H
L
UB
1
X
X
H
H
L
L
H
L
L
Mode
Not selected
Output disabled
Output disabled
Lower Byte Read
Upper Byte Read
Word Read
Lower Byte Write
Upper Byte Write
Word Write
V
DD
Current
I
SB1
, I
SB2
I
DDR
I
DDR
I
DDR
I
DDR
I
DDR
I
DDW
I
DDW
I
DDW
DQL[7:0]
2
Hi-Z
Hi-Z
Hi-Z
D
Out
Hi-Z
D
Out
D
in
Hi-Z
D
in
DQU[15:8]
2
Hi-Z
Hi-Z
Hi-Z
Hi-Z
D
Out
D
Out
Hi-Z
D
in
D
in
Notes:
1. H = high, L = low, X = don’t care
2. Hi-Z = high impedance
Copyright © 2015 Everspin Technologies
5
MR0A16A Rev. 8.2, 6/2015
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