FemtoClock
®
Crystal-to-LVDS
Clock Generator
G
ENERAL
D
ESCRIPTION
The 844008I-46 is a 10Gb Ethernet Clock Generator and a member
of the HiPerClocks™ family of high performance devices from
IDT. The 844008I-46 can synthesize 156.25MHz or 100MHz with
a 25MHz crystal. It has a total of 8 LVDS outputs. The 844008I-46
has excellent phase jitter performance and is packaged in a 32
Lead VFQFN package, making it ideal for use in systems with
limited board space.
844008I-46
DATA SHEET
F
EATURES
• Eight differential LVDS outputs
• Crystal oscillator interface designed for 18pF parallel resonant
crystals
• Supports the following output frequencies:
156.25MHz or 100MHz
• VCO frequency: 625MHz or 600MHz
• RMS phase jitter @ 156.25MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.45ps (typical)
• Full 2.5V supply mode
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) packages
• For functional replacement part use 8T49N285
F
REQUENCY
S
ELECT
F
UNCTION
T
ABLE
Input
XTAL Frequency
(MHz)
25
25
FREQ_SEL
0
1
FB Divider
÷25
÷24
Output Divider
÷4
÷6
VCO (MHz)
625
600
Output Frequency (MHz)
156.25 (default)
100
B
LOCK
D
IAGRAM
OE
Pullup
25MHz
8
P
IN
A
SSIGNMENT
FREQ_SEL
XTAL_OUT
XTAL_IN
GND
V
DDA
V
DD
XTAL_IN
OSC
Phase
Detector
VCO
625MHz or
600MHz
÷4
or
÷6
Q0:Q7
nQ0:nQ7
Q0
nQ0
1
2
3
4
nc
nc
8
XTAL_OUT
32 31 30 29 28 27 26 25
24
nc
OE
GND
nQ7
Q7
V
DDO
nQ6
Q6
FB =
÷
25 or
÷
24
GND
Q1
nQ1
V
DDO
Q2
nQ2
ICS844008I-46
23
22
FREQ_SEL
Pulldown
32-Lead VFQFN
21
5mm x 5mm x 0.925mm pack-
5
20
age body
6
19
K Package
7
Top View
18
8
9 10 11 12 13 14 15 16
Q3
nQ3
GND
Q4
nQ4
Q5
V
DDO
nQ5
17
844008I-46 REVISION A 11/6/15
1
©2015 Integrated Device Technology, Inc.
844008I-46 DATA SHEET
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2
3, 11, 22, 32
4, 5
6, 14, 19
7, 8
9, 10
12, 13
15, 16
17, 18
20, 21
23
24, 28, 29
25
26
27
30,
31
Name
Q0, nQ0
GND
Q1, nQ1
V
DDO
Q2, nQ2
Q3, nQ3
Q4, nQ4
Q5, nQ5
Q6, nQ6
Q7, nQ7
OE
nc
V
DDA
FREQ_SEL
V
DD
XTAL_IN,
XTAL_OUT
Power
Ouput
Power
Output
Output
Output
Output
Output
Output
Input
Unused
Power
Input
Power
Input
Pullup
Type
Output
Description
Differential output pair. LVDS interface levels.
Power supply ground.
Differential output pair. LVDS interface levels.
Output supply pins.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Output enable pin. When LOW, outputs are disabled. When HIGH. outputs
are enabled. LVCMOS/LVTTL interface levels. See Table 3.
No connect.
Analog supply pin.
Pulldown Frequency select pin. LVCMOS/LVTTL interface levels.
Core supply pin.
Parallel resonant crystal interface. XTAL_OUT is the output,
XTAL_IN is the input.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLDOWN
R
PULLUP
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
T
ABLE
3. OE F
UNCTION
T
ABLE
Inputs
OE
1
0
Outputs
Q[0:7]/nQ[0:7]
Enabled (default)
Hi-Z
FEMTOCLOCK™ CRYSTAL-TO-LVDS
CLOCK GENERATOR
2
REVISION A 11/6/15
844008I-46 DATA SHEET
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
(LVDS)
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+ 0.5V
10mA
15mA
37°C/W (0 mps)
-65°C to 150°C
N OT E : S t r e s s e s b eyo n d t h o s e l i s t e d u n d e r A b s o l u t e
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
2.375
V
DD
– 0.25
2.375
Typical
2.5
2.5
2.5
Maximum
2.625
V
DD
2.625
60
25
140
Units
V
V
V
mA
mA
mA
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
OE
FREQ_SEL
OE
FREQ_SEL
V
DD
= V
IN
= 2.625
V
DD
= V
IN
= 2.625
V
DD
= 2.625V, V
IN
= 0V
V
DD
= 2.625V, V
IN
= 0V
-150
-5
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
5
150
Units
V
V
µA
µA
µA
µA
T
ABLE
4C. LVDS DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
V
OD
Δ
V
OD
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
Test Conditions
Minimum
247
1.10
Typical
340
1.25
Maximum
454
50
1.375
50
Units
mV
mV
V
mV
V
OS
Δ
V
OS
REVISION A 11/6/15
3
FEMTOCLOCKS™ CRYSTAL-TO-LVDS
CLOCK GENERATOR
844008I-46 DATA SHEET
T
ABLE
5. C
RYSTAL
C
HARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
NOTE: Characterized using an 18pF parallel resonant crystal.
Test Conditions
Minimum
Typical
25
50
7
300
Maximum
Units
MHz
Ω
pF
µW
Fundamental
T
ABLE
6. AC C
HARACTERISTICS
,
V
DD
= V
DDO
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
f
OUT
tsk(o)
tjit(cc)
tjit(Ø)
t
R
/ t
F
odc
Parameter
Output Frequency
Output Skew; NOTE 1, 2
Cycle-to-Cycle Jitter
RMS Phase Jitter (Random);
NOTE 3
Output Rise/Fall Time
Output Duty Cycle
156.25MHz (1.875MHz - 20MHz)
100MHz (1.875MHz - 20MHz)
20% to 80%
300
48
0.45
0.52
700
52
Test Conditions
FREQ_SEL = 0
FREQ_SEL = 1
Minimum
Typical
156.25
100
75
20
Maximum
Units
MHz
MHz
ps
ps
ps
ps
ps
%
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at the differential cross points.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plot.
FEMTOCLOCK™ CRYSTAL-TO-LVDS
CLOCK GENERATOR
4
REVISION A 11/6/15
844008I-46 DATA SHEET
T
YPICAL
P
HASE
N
OISE AT
156.25MH
Z
➤
Ethernet Filter
156.25MHz
RMS Phase Jitter (Random)
1.875Mhz to 20MHz = 0.45ps (typical)
N
OISE
P
OWER
dBc
Hz
Raw Phase Noise Data
➤
➤
10Gb Ethernet Filter
➤
➤
Phase Noise Result by adding
Ethernet Filter to raw data
O
FFSET
F
REQUENCY
(H
Z
)
T
YPICAL
P
HASE
N
OISE AT
100MH
Z
100MHz
RMS Phase Jitter (Random)
1.875Mhz to 20MHz = 0.52ps (typical)
Raw Phase Noise Data
➤
Phase Noise Result by adding a
10Gb Ethernet Filter to raw data
O
FFSET
F
REQUENCY
(H
Z
)
REVISION A 11/6/15
5
FEMTOCLOCKS™ CRYSTAL-TO-LVDS
CLOCK GENERATOR
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