W255
200 MHz 24-Output Buffer for 4 DDR or 3 SDRAM DIMMS
Features
• One input to 24 output buffer/driver
• Supports up to 4 DDR DIMMs or 3 SDRAM DIMMS
• One additional output for feedback
• SMBus interface for individual output control
• Low skew outputs (< 100 ps)
• Supports 266-, 333-, and 400 MHz DDR SDRAM
• Dedicated pin for power management support
• Space-saving 48-pin SSOP package
Functional Description
The W255 is a 3.3V/2.5V buffer designed to distribute
high-speed clocks in PC applications. The part has 24 outputs.
Designers can configure these outputs to support four unbuf-
fered DDR DIMMS or to support three unbuffered standard
SDRAM DIMMs and two DDR DIMMS. The W255 can be used
in conjunction with the W250 or similar clock synthesizer for
the VIA Pro 266 chipset.
The W255 also includes an SMBus interface which can enable
or disable each output clock. On power-up, all output clocks
are enabled (internal pull up).
Block Diagram
FBOUT
BUF_IN
DDR0T_SDRAM10
DDR0C_SDRAM11
DDR1T_SDRAM0
DDR1C_SDRAM1
DDR2T_SDRAM2
DDR2C_SDRAM3
DDR3T_SDRAM4
DDR3C_SDRAM5
DDR4T_SDRAM6
DDR4C_SDRAM7
DDR5T_SDRAM8
DDR5C_SDRAM9
DDR6T
DDR6C
DDR7T
DDR7C
DDR8T
DDR8C
DDR9T
DDR9C
DDR10T
PWR_DWN#
Power Down Control
Pin Configuration
[1]
SSOP
Top View
FBOUT
VDD3.3_2.5
GND
DDR0T_SDRAM10
DDR0C_SDRAM11
DRR1T_SDRAM0
DDR1C_SDRAM1
VDD3.3_2.5
GND
DDR2T_SDRAM2
DDR2C_SDRAM3
VDD3.3_2.5
BUF_IN
GND
DDR3T_SDRAM4
DDR3C_SDRAM5
VDD3.3_2.5
GND
DDR4T_SDRAM6
DDR4C_SDRAM7
DDR5T_SDRAM8
DDR5C_SDRAM9
VDD3.3_2.5
SDATA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
SDATA
SMBus
Decoding
SCLOCK
DDR10C
DDR11T
DDR11C
SEL_DDR*
VDD2.5
GND
DDR11T
DDR11C
DDR10T
DDR10C
VDD2.5
GND
DDR9T
DDR9C
VDD2.5
PWR_DWN#*
GND
DDR8T
DDR8C
VDD2.5
GND
DDR7T
DDR7C
DDR6T
DDR6C
GND
SCLK
SEL_DDR
Note:
1. Internal 100K pull-up resistors present on inputs marked
with *. Design should not rely solely on internal pull-up resistor
to set I/O pins HIGH.
.......................... Document #: 38-07255 Rev. *D Page 1 of 9
400 West Cesar Chavez, Austin, TX 78701
1+(512) 416-8500
1+(512) 416-9669
www.silabs.com
W255
Pin Summary
Pin Name
SEL_DDR
Pins
48
Pin Description
Input to configure for DDR-ONLY mode or STANDARD SDRAM
mode.
1 = DDR-ONLY mode.
0 = STANDARD SDRAM mode.
When SEL_DDR is pulled HIGH or configured for DDR-ONLY mode, pin
4, 5, 6, 7, 10, 11,15, 16, 19, 20, 21, 22, 27, 28, 29, 30, 33, 34, 38, 39,
42, 43, 44 and 45 will be configured as DDR outputs.
Connect VDD3.3_2.5 to a 2.5V power supply in DDR-ONLY mode.
When SEL_DDR is pulled LOW or configured for STANDARD SDRAM
output, pin 4, 5, 6, 7, 10, 11, 15, 16, 19 and 20, 21, 22 will be configured
as STANDARD SDRAM outputs.Pin 27, 28, 29, 30, 33, 34, 38, 39, 42,
43, 44 and 45 will be configured as DDR outputs.
Connect VDD3.3_2.5 to a 3.3V power supply in STANDARD SDRAM
mode.
SCLK
SDATA
BUF_IN
FBOUT
PWR_DWN#
DDR[6:11]T
DDR[6:11]C
DDR[0:5]T_SDRAM
[10,0,2,4,6,8]
25
24
13
1
36
28, 30, 34, 39, 43, 45
27, 29, 33, 38, 42, 44
4, 6, 10, 15, 19, 21
SMBus clock input
SMBus data input
Reference input from chipset.
2.5V input for DDR-ONLY mode; 3.3V
input for STANDARD SDRAM mode.
Feedback clock for chipset.
Output voltage depends on VDD3.3_2.5V.
Active LOW input to enable power-down mode;
all outputs will be
pulled LOW.
Clock outputs.
These outputs provide copies of BUF_IN.
Clock outputs.
These outputs provide complementary copies of
BUF_IN.
Clock outputs.
These outputs provide copies of BUF_IN. Voltage swing
depends on VDD3.3_2.5 power supply.
Clock outputs.
These outputs provide complementary copies of
BUF_IN when SEL_DDR is active. These outputs provide copies of
BUF_IN when SEL_DDR is inactive. Voltage swing depends on
VDD3.3_2.5 power supply.
Connect to 2.5V power supply
when W255 is configured for
DDR-ONLY mode. Connect to 3.3V power supply, when W255 is
configured for standard SDRAM mode.
2.5V voltage supply
DDR[0:5]C_SDRAM 5, 7, 11, 16, 20, 22
[11,1,3,5,7,9]
VDD3.3_2.5
2, 8, 12, 17, 23
VDD2.5
GND
32, 37, 41, 47
3, 9, 14, 18, 26, 31, 35, 40, 46
Ground
..........................Document #: 38-07255 Rev. *D Page 2 of 9
W255
Serial Configuration Map
• The serial bits will be read by the clock driver in the following
order:
Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0
.
.
Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0
• Reserved and unused bits should be programmed to “0.”
• SMBus Address for the W255 is:
Table 1.
A6
1
A5
1
A4
0
A3
1
A2
0
A1
0
A0
1
R/W
----
Bit 2
Bit 1
Bit 0
10, 11
6, 7
4, 5
Byte 7: Outputs Active/Inactive Register
(1 = Active, 0 = Inactive), Default = Active
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Pin #
30, 29
28, 27
21, 22
19, 20
15,16
Description
DDR7T, DDR7C
DDR6T, DDR6C
DDR5T_SDRAM8,
DDR5C_SDRAM9
DDR4T_SDRAM6,
DDR4C_SDRAM7
DDR3T_SDRAM4,
DDR3C_SDRAM5
DDR2T_SDRAM2,
DDR2C_SDRAM3
DDR1T_SDRAM0,
DDR1C_SDRAM1
DDR0T_SDRAM10,
DDR0C_SDRAM11
1
1
1
1
1
1
1
1
Default
Byte 6: Outputs Active/Inactive Register
(1 = Active, 0 = Inactive), Default = Active
Bit
Pin #
Description
Reserved, drive to 0
Reserved, drive to 0
Reserved, drive to 0
FBOUT
DDR11T, DDR11C
Default
0
0
0
1
1
1
1
1
Bit 7 –
Bit 6 –
Bit 5 –
Bit 4 1
Bit 3 45,44
Bit 2 43, 42 DDR10T, DDR10C
Bit 1 39, 38 DDR9T, DDR9C
Bit 0 34, 33 DDR8T, DDR8C
..........................Document #: 38-07255 Rev. *D Page 3 of 9
W255
Maximum Ratings
Supply Voltage to Ground Potential..................–0.5 to +7.0V
DC Input Voltage (except BUF_IN)............ –0.5V to V
DD
+0.5
Storage Temperature...................................–65°C to +150°C
Static Discharge Voltage .......................................... > 2000V
(per MIL-STD-883, Method 3015)
Operating Conditions
[2]
Parameter
VDD3.3
VDD2.5
T
A
C
OUT
C
IN
Supply Voltage
Supply Voltage
Operating Temperature (Ambient Temperature)
Output Capacitance
Input Capacitance
Description
Min.
3.135
2.375
0
6
5
Typ.
Max.
3.465
2.625
70
Unit
V
V
°C
pF
pF
Electrical Characteristics
Over the Operating Range
Parameter
V
IL
V
IH
I
IL
I
IH
I
OH
I
OL
V
OL
V
OH
I
DD
I
DD
I
DDS
V
OUT
V
OC
IN
DC
Description
Input LOW Voltage
Input HIGH Voltage
Input LOW Current
Input HIGH Current
Output HIGH Current
Output LOW Current
Output LOW Voltage
[3]
Output HIGH Voltage
[3]
Supply
(DDR-only mode)
Supply Current
(DDR-only mode)
Supply Current
Output Voltage Swing
Output Crossing Voltage
Input Clock Duty Cycle
[4]
Test Conditions
For all pins except SMBus
Min.
2.0
Typ.
Max.
0.8
50
50
Unit
V
V
A
A
mA
mA
V
IN
= 0V
V
IN
= V
DD
V
DD
= 2.375V
V
OUT
= 1V
V
DD
= 2.375V
V
OUT
= 1.2V
I
OL
= 12 mA, V
DD
= 2.375V
I
OH
= –12 mA, V
DD
= 2.375V
Unloaded outputs, 133 MHz
Loaded outputs, 133 MHz
PWR_DWN# = 0
See test circuity (refer to
Figure 1)
0.7
(V
DD
/2) –
0.1
48
V
DD
/2
1.7
–18
26
–32
35
0.6
400
500
100
V
DD
+0.6
(V
DD
/2) +
0.1
52
V
V
mA
mA
A
V
V
%
Current
[3]
Switching Characteristics
Parameter
–
–
t
3
t
4
t
3d
Name
Operating Frequency
Test Conditions
Measured at 1.4V for 3.3V outputs
Measured at V
DD
/2 for 2.5V outputs
Measured between 0.4V and 2.4V
Measured between 2.4V and 0.4V
Measured between 20% to 80% of
output (refer to
Figure 1)
Min.
66
IN
DC
–
5%
1.0
1.0
0.5
Typ.
Max.
200
IN
DC
+
5%
2.75
2.75
1.50
Unit
MHz
%
V/ns
V/ns
V/ns
Duty Cycle
[3, 5]
= t
2
t
1
SDRAM Rising Edge Rate
[3]
SDRAM Falling Edge Rate
[3]
DDR Rising Edge Rate
[3]
Notes:
2.
Multiple Supplies:
The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
3. Parameter is guaranteed by design and characterization. Not 100% tested in production.
4. All parameters specified with loaded outputs.
5. Duty cycle of input clock is 50%. Rising and falling edge rate is greater than 1 V/ns.
..........................Document #: 38-07255 Rev. *D Page 4 of 9
W255
Switching Characteristics
(continued)
[4]
Parameter
t
4d
t
5
t
6
t
7
t
8
Name
DDR Falling Edge Rate
[3]
Test Conditions
Measured between 20% to 80% of
output (refer to
Figure 1)
All outputs equally loaded
Input edge greater than 1 V/ns
Input edge greater than 1 V/ns
5
5
Min.
0.5
Typ.
Max.
1.50
100
150
10
10
Unit
V/ns
ps
ps
ns
ns
Output to Output Skew for DDR
[3]
All outputs equally loaded
Output to Output Skew for
SDRAM
[3]
SDRAM Buffer LH Prop. Delay
[3]
SDRAM Buffer HL Prop. Delay
[3]
Switching Waveforms
Duty Cycle Timing
t
1
t
2
All Outputs Rise/Fall Time
2.4V
0.4V
t
3
2.4V
0.4V
t
4
3.3V
0V
OUTPUT
Output-Output Skew
OUTPUT
OUTPUT
t
5
SDRAM Buffer HH and LL Propagation Delay
1.5V
INPUT
OUTPUT
t
6
1.5V
t
7
..........................Document #: 38-07255 Rev. *D Page 5 of 9
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