74LVC374A
OCTAL D-TYPE FLIP-FLOP
HIGH PERFORMANCE
s
s
s
s
s
s
s
s
s
s
5V TOLERANT INPUTS
HIGH SPEED: t
PD
= 6.8ns (MAX.) at V
CC
= 3V
POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 24mA (MIN) at V
CC
= 3V
PCI BUS LEVELS GUARANTEED AT 24 mA
BALANCED PROPAGATION DELAYS:
t
PLH
≅
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 1.65V to 3.6V (1.2V Data
Retention)
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 374
LATCH-UP PERFORMANCE EXCEEDS
500mA (JESD 17)
ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
SOP
TSSOP
Table 1: Order Codes
PACKAGE
SOP
TSSOP
DESCRIPTION
The 74LVC374A is an advanced high-speed
CMOS OCTAL D-TYPE FLIP FLOP with 3 STATE
OUTPUTS NON INVERTING fabricated with
sub-micron silicon gate and double-layer metal
wiring C
2
MOS technology.
These 8 bit D-Type latch are controlled by a clock
input (CK) and an output enable input (OE).
On the positive transition of the clock, the Q
outputs will be set to the logic state that were
setup at the D inputs.
Figure 1: Pin Connection And IEC Logic Symbols
te
le
so
b
O
ro
P
uc
d
s)
t(
While the (OE) input is low, the 8 outputs will be in
a normal logic state (high or low logic level) and
while high level the outputs will be in a high
impedance state.
The Output control does not affect the internal
operation of flip flops; that is, the old data can be
retained or the new data can be entered even
while the outputs are off. Power down protection is
provided on all inputs and 0 to 7V can be accepted
on inputs with no regard to the supply voltage.
This device can be used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
O
-
so
b
t
le
r
P
e
du
o
T&R
s)
t(
c
74LVC374AMTR
74LVC374ATTR
July 2004
Rev. 2
1/14
74LVC374A
Figure 2: Input And Output Equivalent Circuit
Table 2: Pin Description
PIN N°
1
2, 5, 6, 9, 12, 15, 16,19
3, 4, 7, 8, 13, 14, 17, 18
11
10
20
SYMBOL
OE
Q0 to Q7
D0 to D7
CK
GND
V
CC
NAME AND FUNCTION
3 State Output Enable Input (Active LOW)
3-State Outputs
Data Inputs
Clock
Ground (0V)
Positive Supply Voltage
Table 3: Truth Table
INPUTS
OE
H
X : Don’t Care
Z :High Impedance
et
l
so
b
O
L
L
L
P
e
ro
uc
d
CK
X
s)
t(
O
-
so
b
D
X
X
L
H
t
le
r
P
e
du
o
s)
t(
c
OUTPUT
Q
Z
NO CHANGE
L
H
2/14
74LVC374A
Table 4: Absolute Maximum Ratings
Symbol
V
CC
V
I
V
O
V
O
I
IK
I
OK
I
O
Supply Voltage
DC Input Voltage
DC Output Voltage (V
CC
= 0V)
DC Output Voltage (High or Low State) (note 1)
DC Input Diode Current
DC Output Diode Current (note 2)
DC Output Current
Parameter
Value
-0.5 to +7.0
-0.5 to +7.0
-0.5 to +7.0
-0.5 to V
CC
+ 0.5
- 50
- 50
±
50
±
100
-65 to +150
300
Unit
V
V
V
V
mA
mA
mA
I
CC
or I
GND
DC V
CC
or Ground Current per Supply Pin
Storage Temperature
T
stg
T
L
Lead Temperature (10 sec)
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
1) I
O
absolute maximum rating must be observed
2) V
O
< GND
Table 5: Recommended Operating Conditions
Symbol
V
CC
V
I
V
O
V
O
I
OH
, I
OL
I
OH
, I
OL
I
OH
, I
OL
I
OH
, I
OL
T
op
dt/dv
Supply Voltage (note 1)
Input Voltage
Output Voltage (V
CC
= 0V)
Output Voltage (High or Low State)
Parameter
High or Low Level Output Current (V
CC
= 3.0 to 3.6V)
High or Low Level Output Current (V
CC
= 2.7 to 3.0V)
High or Low Level Output Current (V
CC
= 2.3 to 2.7V)
High or Low Level Output Current (V
CC
= 1.65 to 2.3V)
Operating Temperature
Input Rise and Fall Time (note 2)
1) Truth Table guaranteed: 1.2V to 3.6V
2) V
I
from 0.8V to 2V at V
CC
= 3.0V
te
le
so
b
O
ro
P
uc
d
)-
(s
t
b
O
so
t
le
r
P
e
Value
1.65 to 3.6
0 to 5.5
0 to 5.5
0 to V
CC
±
24
±
12
±
8
±
4
-55 to 125
0 to 10
du
o
s)
t(
c
mA
°C
°C
Unit
V
V
V
V
mA
mA
mA
mA
°C
ns/V
3/14
74LVC374A
Table 6: DC Specifications
Test Condition
Symbol
Parameter
V
CC
(V)
1.65 to 1.95
2.3 to 2.7
2.7 to 3.6
1.65 to 1.95
2.3 to 2.7
2.7 to 3.6
1.65 to 3.6
1.65
2.3
2.7
3.0
3.0
V
OL
Low Level Output
Voltage
1.65 to 3.6
1.65
2.3
2.7
3.0
I
I
I
off
I
OZ
Input Leakage
Current
Power Off Leakage
Current
High Impedance
Output Leakage
Current
Quiescent Supply
Current
I
CC
incr. per Input
3.6
0
I
O
=-100
µA
I
O
=-4 mA
I
O
=-8 mA
I
O
=-12 mA
I
O
=-18 mA
I
O
=-24 mA
I
O
=100
µA
I
O
=4 mA
I
O
=8 mA
I
O
=12 mA
V
CC
-0.2
1.2
1.7
2.2
2.4
2.2
-40 to 85 °C
Min.
0.65V
CC
1.7
2
0.35V
CC
0.7
0.8
V
CC
-0.2
1.2
1.7
Max.
Value
-55 to 125 °C
Min.
0.65V
CC
1.7
2
0.35V
CC
0.7
0.8
V
V
Max.
Unit
V
IH
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
V
IL
V
OH
3.6
∆I
CC
Table 7: Dynamic Switching Characteristics
Test Condition
V
CC
(V)
3.3
C
L
= 50pF
V
IL
= 0V, V
IH
= 3.3V
Value
T
A
= 25 °C
Min.
Typ.
0.8
-0.8
Max.
V
Unit
te
le
so
b
O
I
CC
ro
P
uc
d
V
I
or V
O
= 5.5V
V
I
= V
IH
or V
IL
V
O
= 0 to 5.5V
)-
(s
t
I
O
=24 mA
V
I
= 0 to 5.5V
b
O
so
t
le
0.2
0.45
0.7
0.4
0.55
±
5
10
±
10
ro
P
e
2.2
2.4
2.2
du
s)
t(
c
V
V
0.2
0.7
0.45
0.4
0.55
±
5
10
±
10
µA
µA
µA
V
I
= V
CC
or GND
V
I
or V
O
= 3.6 to
5.5V
V
IH
= V
CC
-0.6V
10
±
10
500
10
±
10
500
µA
µA
3.6
2.7 to 3.6
Symbol
Parameter
V
OLP
V
OLV
Dynamic Low Level Quiet
Output (note 1)
1) Number of output defined as "n". Measured with "n-1" outputs switching from HIGH to LOW or LOW to HIGH. The remaining output is
measured in the LOW state.
4/14
74LVC374A
Table 8: AC Electrical Characteristics
Test Condition
Symbol
Parameter
V
CC
(V)
C
L
(pF)
30
30
50
50
30
30
50
50
30
30
50
50
30
30
50
50
30
30
50
50
30
30
50
50
30
30
50
50
R
L
(Ω)
1000
500
500
500
1000
500
500
500
1000
500
500
500
1000
500
500
500
1000
500
500
500
1000
500
500
500
1000
500
500
500
t
s
=
t
r
(ns)
2.0
2.0
2.5
2.5
2.0
2.0
2.5
2.5
2.0
2.0
2.5
2.5
2.0
2.0
2.5
2.5
2.0
2.0
2.5
2.5
2.0
2.0
2.5
2.5
2.0
2.0
2.5
2.5
-40 to 85 °C
Min.
Max.
TBD
TBD
7.8
6.8
TBD
TBD
7.8
6.8
TBD
TBD
8.7
7.7
TBD
TBD
7.6
7.0
Value
-55 to 125 °C
Min.
Max.
TBD
TBD
9.4
8.2
TBD
TBD
9.4
8.2
TBD
TBD
10.4
9.2
TBD
TBD
9.1
8.4
Unit
t
PLH
t
PHL
Propagation Delay
Time D to Q
t
PLH
t
PHL
t
PZL
t
PZH
t
PLZ
t
PHZ
t
W
t
s
t
h
t
OSLH
t
OSHL
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW (t
OSLH
= | t
PLHm
- t
PLHn
|, t
OSHL
= | t
PHLm
- t
PHLn
|
2) Parameter guaranteed by design
et
l
so
b
O
1.65 to 1.95
2.3 to 2.7
2.7
3.0 to 3.6
Propagation Delay
1.65 to 1.95
Time LE to Q
2.3 to 2.7
2.7
3.0 to 3.6
Output Enable Time 1.65 to 1.95
2.3 to 2.7
2.7
3.0 to 3.6
Output Disable Time 1.65 to 1.95
2.3 to 2.7
2.7
3.0 to 3.6
LE Pulse Width
1.65 to 1.95
HIGH
2.3 to 2.7
2.7
3.0 to 3.6
Setup Time D to LE 1.65 to 1.95
(HIGH to LOW)
2.3 to 2.7
2.7
3.0 to 3.6
Hold Time D to
1.65 to 1.95
CLOCK, HIGH or
2.3 to 2.7
LOW
2.7
3.0 to 3.6
Output To Output
2.7 to 3.6
Skew Time (note1,
2)
1.5
1
1.5
1
ns
1.5
1
1.5
1
1
1
P
e
od
r
uc
s)
t(
O
-
so
b
2
2
TBD
TBD
3.3
3.3
TBD
TBD
2
2
TBD
TBD
1.5
1.5
t
le
r
P
e
2
2
TBD
TBD
3.3
3.3
TDB
TBD
2
2
TBD
TBD
1.5
1.5
1
1
du
o
s)
t(
c
ns
ns
ns
ns
ns
ns
1
1
ns
Table 9: Capacitive Characteristics
Test Condition
Symbol
Parameter
V
CC
(V)
Value
T
A
= 25 °C
Min.
f
IN
= 10MHz
Typ.
4
1.8
2.5
3.3
28
30
34
Max.
pF
pF
Unit
C
IN
C
PD
Input Capacitance
Power Dissipation Capacitance
(note 1)
1) C
PD
is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
/n (per circuit)
5/14
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