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74LCX16501 Low Voltage 18-Bit Universal Bus Transceivers with 5V Tolerant Inputs and Outputs
October 1995
Revised March 2001
74LCX16501
Low Voltage 18-Bit Universal Bus Transceivers
with 5V Tolerant Inputs and Outputs
General Description
The LCX16501 is an 18-bit universal bus transceiver com-
bining D-type latches and D-type flip-flops to allow data
flow in transparent, latched, and clocked modes.
Data flow in each direction is controlled by output-enable
(OEAB and OEBA), latch-enable (LEAB and LEBA), and
clock (CLKAB and CLKBA) inputs.
The LCX16501 is designed for low voltage (2.5V or 3.3V)
V
CC
applications with capability of interfacing to a 5V signal
environment.
The LCX16501 is fabricated with an advanced CMOS tech-
nology to achieve high speed operation while maintaining
CMOS low power.
Features
s
5V tolerant inputs and outputs
s
2.3V–3.6V V
CC
specifications provided
s
6.0 ns t
PD
max (V
CC
=
3.3V), 20
µ
A I
CC
max
s
Power down high impedance inputs and outputs
s
Supports live insertion/withdrawal (Note 1)
s
±
24 mA Output Drive (V
CC
=
3.0V)
s
Implements patented noise/EMI reduction circuitry
s
Latch-up performance exceeds 500 mA
s
ESD performance:
Human body model
>
2000V
Machine model
<
200V
Note 1:
To ensure the high-impedance state during power up or down, OE
should be tied to V
CC
and OE tied to GND through a resistor: the minimum
value or the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Order Number
74LCX16501MEA
74LCX16501MTD
Package Number
MS56A
MTD56
Package Description
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
A-to-B data flow is shown: B-to-A flow is similar but uses OEBA,
LEBA, and CLKBA.
Note 3:
Output level before the indicated steady-state input conditions
were established, provided that CLKAB was HIGH before LEAB went LOW.
Note 4:
Output level before the indicated steady-state input conditions
were established.
Functional Description
For A-to-B data flow, the LCX16501 operates in the trans-
parent mode when LEAB is HIGH. When LEAB is LOW,
the A data is latched if CLKAB is held at a high or low logic
level. If LEAB is LOW, the A bus data is stored in the latch/
flip-flop on the LOW-to-HIGH transition of CLKAB. When
OEAB is HIGH, the outputs are active. When OEAB is
LOW, the outputs are in the high impedance state.
Data flow for B to A is similar to that of A to B but uses
OEBA, LEBA, and CLKBA. The output enables are com-
plementary (OEAB is active HIGH and OEBA is active
LOW).
Logic Diagram
www.fairchildsemi.com
2
74LCX16501
Absolute Maximum Ratings
(Note 5)
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
I
GND
T
STG
Parameter
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Source/Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
Value
Conditions
Units
V
V
Output in 3-STATE
Output in HIGH or LOW State (Note 6)
V
I
<
GND
V
O
<
GND
V
O
>
V
CC
V
mA
mA
mA
mA
mA
−
0.5 to
+
7.0
−
0.5 to
+
7.0
−
0.5 to
+
7.0
−
0.5 to V
CC
+
0.5
−
50
−
50
+
50
±
50
±
100
±
100
−
65 to
+
150
°
C
Recommended Operating Conditions
(Note 7)
Symbol
V
CC
V
I
V
O
I
OH
/I
OL
Supply Voltage
Input Voltage
Output Voltage
Output Current
HIGH or LOW State
3-STATE
V
CC
=
3.0V
−
3.6V
V
CC
=
2.7V
−
3.0V
V
CC
=
2.3V
−
2.7V
T
A
Free-Air Operating Temperature
Input Edge Rate, V
IN
=
0.8V–2.0V, V
CC
=
3.0V
Parameter
Operating
Data Retention
Min
2.0
1.5
0
0
0
Max
3.6
3.6
5.5
V
CC
5.5
Units
V
V
V
±
24
±
12
±
8
−
40
0
85
10
mA
°
C
ns/V
∆
t/
∆
V
Note 5:
The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated
at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recom-
mended Operating Conditions” table will define the conditions for actual device operation.
Note 6:
I
O
Absolute Maximum Rating must be observed.
Note 7:
Unused (inputs or I/Os) must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
OH
Parameter
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Voltage
I
OH
= −100 µA
I
OH
= −8
mA
I
OH
= −12
mA
I
OH
= −18
mA
I
OH
= −24
mA
V
OL
LOW Level Output Voltage
I
OL
=
100
µA
I
OL
=
8 mA
I
OL
=
12 mA
I
OL
=
16 mA
I
OL
=
24 mA
I
I
I
OZ
I
OFF
Input Leakage Current
3-STATE I/O Leakage
Power-Off Leakage Current
0
≤
V
I
≤
5.5V
0
≤
V
O
≤
5.5V
V
I
=
V
IH
or V
IL
V
I
or V
O
=
5.5V
0
10
Conditions
V
CC
(V)
2.3
−
2.7
2.7
−
3.6
2.3
−
2.7
2.7
−
3.6
2.3
−
3.6
2.3
2.7
3.0
3.0
2.3
−
3.6
2.3
2.7
3.0
3.0
2.3
−
3.6
2.3
−
3.6
V
CC
−
0.2
1.8
2.2
2.4
2.2
0.2
0.6
0.4
0.4
0.55
±5.0
±5.0
µA
µA
µA
V
V
T
A
= −40°C
to
+85°C
Min
1.7
2.0
0.7
0.8
Max
Units
V
V
3
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74LCX16501
DC Electrical Characteristics
Symbol
I
CC
∆I
CC
Parameter
Quiescent Supply Current
Increase in I
CC
per Input
(Continued)
V
CC
(V)
2.3
−
3.6
2.3
−
3.6
2.3− 3.6
T
A
= −40°C
to
+85°C
Min
Max
20
±20
500
µA
µA
Conditions
V
I
=
V
CC
or GND
3.6V
≤
V
I
, V
O
≤
5.5V (Note 8)
V
IH
=
V
CC
−0.6V
Units
Note 8:
Outputs disabled or 3-STATE only.
AC Electrical Characteristics
T
A
= −40°C
to
+85°C,
R
L
=
500Ω
Symbol
Parameter
V
CC
=
3.3V
±
0.3V
C
L
=
50 pF
Min
f
MAX
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PZL
t
PZH
t
PLZ
t
PHZ
t
S
t
H
t
W
t
OSHL
t
OSLH
Setup Time
Hold Time
Pulse Width
Output to Output Skew
(Note 9)
Output Disable Time
Maximum Clock Frequency
Propagation Delay
Bus to Bus
Propagation Delay
Clock to Bus
Propagation Delay
LE to Bus
Output Enable Time
170
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
2.5
1.5
3.0
1.0
1.0
6.0
6.0
6.7
6.7
7.0
7.0
7.2
7.2
7.0
7.0
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
2.5
1.5
3.0
7.0
7.0
8.0
8.0
8.0
8.0
8.2
8.2
8.0
8.0
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
3.0
2.0
3.5
7.2
7.2
8.4
8.4
8.4
8.4
9.4
9.4
8.4
8.4
Max
V
CC
=
2.7V
C
L
=
50 pF
Min
Max
V
CC
=
2.5V
±
0.2V
C
L
=
30 pF
Min
Max
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
Note 9:
Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t