74LV132A
QUADRUPLE 2-INPUT NAND GATES WITH SCHMITT TRIGGER INPUTS
Description
The 74LV132A provides provides four independent 2-input NAND
gates with standard push-pull outputs. Each input is a Schmitt Trigger
device with a significant amount of hysteresis suiting the device for
noisy environments. The device is designed for operation with a
power supply range of 2.0V to 5.5V.
The inputs are tolerant to 5.5V allowing this device to be used in a
mixed voltage environment. The device is fully specified for partial
power down applications using I
OFF
. The I
OFF
circuitry disables the
output preventing damaging current backflow when the device is
powered down.
The gates perform the Boolean function:
Pin Assignments
Preliminary
Y
½
A
B
or
Y
½
A
B
Features
Wide Supply Voltage Range from 2.0V to 5.5V
Sinks or sources 12mA at V
CC
= 4.5V
CMOS low power consumption
I
OFF
Supports Partial -Power Down Operation
Inputs or Outputs accept up to 5.5V
Inputs can be driven by 3.3V or 5V allowing for voltage
translation applications.
Schmitt Trigger Action at All Inputs
ESD Protection Tested per JESD 22
Exceeds 200-V Machine Model (A115)
Exceeds 2000-V Human Body Model (A114)
Exceeds 1000-V Charged Device Model (C101)
Latch-Up Exceeds 100mA per JESD 78, Class I
Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2)
Halogen and Antimony Free. “Green” Device (Note 3)
Applications
General Purpose Logic
Power Down Signal Isolation
Wide array of products such as:
PCs, networking, notebooks, ultrabooks, netbooks
Computer peripherals, hard drives, CD/DVD ROM
TV, DVD, DVR, set top box
Notes:
1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS) & 2011/65/EU (RoHS 2) compliant.
2. See http://www.diodes.com/quality/lead_free.html for more information about Diodes Incorporated’s definitions of Halogen- and Antimony-free,
"Green" and Lead-free.
3. Halogen- and Antimony-free "Green” products are defined as those which contain <900ppm bromine, <900ppm chlorine (<1500ppm total Br + Cl)
and <1000ppm antimony compounds.
Click for Ordering Information
74LV132A
Document number: DS35706 Rev. 1 - 2
1 of 9
www.diodes.com
October 2013
© Diodes Incorporated
74LV132A
Pin Descriptions
Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Pin Name
1A
1B
1Y
2A
2B
2Y
GND
3Y
3A
3B
4Y
4A
4B
Vcc
Description
Data Input
Data Input
Data Output
Data Input
Data Input
Data Output
Ground
Data Output
Data Input
Data Input
Data Output
Data Input
Data Input
Supply Voltage
Logic Diagram
1
2
4
5
9
10
12
13
1A
1B
2A
2B
3A
3B
4A
4B
1Y
3
2Y
6
Preliminary
3Y
8
4Y 11
Function Table
Inputs
A
H
L
X
B
H
X
L
Output
Y
L
H
H
Absolute Maximum Ratings
(Note 4)
Symbol
ESD HBM
ESD CDM
ESD MM
V
CC
V
I
I
IK
I
OK
I
O
I
CC
I
GND
T
J
T
STG
P
TOT
Note:
Description
Human Body Model ESD Protection
Charged Device Model ESD Protection
Machine Model ESD Protection
Supply Voltage Range
Input Voltage Range note 4
Input Clamp Current
Output Clamp Current
V
I
< 0V
V
O
< -0V
Rating
2
1
200
-0.5 to 7.0
-0.5 to 7.0
-20
-50
+/- 25
50
-50
-40 to +150
-65 to +150
500
Unit
kV
kV
V
V
V
mA
mA
mA
mA
mA
°C
°C
mW
Continuous Output Current - 0.5V < V
O
V
CC
+ 0.5V
Continuous Current Through Vcc
Continuous Current Through GND
Operating Junction Temperature
Storage Temperature
Total Power Dissipation
4. Stresses beyond the absolute maximum may result in immediate failure or reduced reliability. These are stress values and device
operation should be within recommend values.
74LV132A
Document number: DS35706 Rev. 1 - 2
2 of 9
www.diodes.com
October 2013
© Diodes Incorporated
74LV132A
Switching Characteristics
Symbol
Parameter
Test
Conditions
Figure 1
C
L
=15pF
Figure 1
C
L
=50 pF
V
CC
2.5V ± 0.2V
3.3V ± 0.3V
5.0V ± 0.5V
2.5V ± 0.2V
3.3V ± 0.3V
5.0V ± 0.5V
T
A
= +25°C
Min
–
–
–
–
–
–
Typ.
7.9
5.6
3.9
10.8
7.6
5.3
Max
16.5
11.9
7.7
20.2
15.4
9.7
-40 to +85°C
Min
1
1
1
1
1
1
Max
18.5
14
9
23
17.5
11
-40 to +125°C
Min
1
1
1
1
1
1
Max
18.5
14
9
23
17.5
11
Unit
ns
t
PD
Propagation
Delay A
N
to Y
N
ns
Preliminary
Operating Characteristics
T
A
= +25°C
Parameter
Test
Conditions
F= 10 MHz
C
L
=50pF
V
CC
3.3V
5.0V
TYP
7.5
11.2
Unit
C
pd
Power Dissipation
Capacitance per Gate
pF
Noise Characteristics
V
CC
=3V, C
L
=50pF, T
A
= +25°C
Symbol
V
OL(p)
V
OL(V)
V
OH(V)
V
IH(D)
V
IL(D)
Parameter
Quiet output, maximum dynamic V
OL
Quiet output, minimum dynamic V
OL
Quiet output, minimum dynamic V
OH
High Level dynamic input voltage
Low Level dynamic input voltage
Min
–
–
–
2.31
–
Typ.
0.2
-0.1
3.1
–
–
Max
0.8
-0.8
–
–
0.99
Unit
V
V
V
V
V
Package Characteristics
Symbol
C
i
Parameter
Input Capacitance
Test Conditions
V
i
= V
CC
– or GND
Vcc
2.0 to 5.5V
Min
–
Typ.
3.3
Max
10
Unit
pF
74LV132A
Document number: DS35706 Rev. 1 - 2
4 of 9
www.diodes.com
October 2013
© Diodes Incorporated
74LV132A
Parameter Measurement Information
Preliminary
V
cc
V
I
2.0V to 5.5V
V
CC
Inputs
t
r
/ t
f
<3ns
V
M
V
CC
/ 2
C
L
15pF or 50pF
Voltage Waveform
Pulse Duration
Voltage Waveform
Propagation Delay Times
Inverting and Non Inverting Outputs
Notes: A. Includes test lead and test apparatus capacitance.
B. All pulses are supplied at pulse repetition rate
≤
10MHz
C. Inputs are measured separately one transition per measurement
D. t
PLH
and t
PHL
are the same as t
PD
Figure 1. Load Circuit and Voltage Waveforms
74LV132A
Document number: DS35706 Rev. 1 - 2
5 of 9
www.diodes.com
October 2013
© Diodes Incorporated
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