GTL2018
8-bit LVTTL to GTL transceiver
Rev. 2 — 29 August 2011
Product data sheet
1. General description
The GTL2018 is an octal translating transceiver designed for 3.3 V LVTTL system
interface with a GTL/GTL/GTL+ bus.
The direction pin (DIR) allows the part to function as either a GTL-to-LVTTL sampling
receiver or as an LVTTL-to-GTL interface.
The GTL2018 LVTTL inputs (only) are tolerant up to 5.5 V, allowing direct access to TTL
or 5 V CMOS inputs.
2. Features and benefits
Operates as an octal GTL/GTL/GTL+ sampling receiver or as an LVTTL to
GTL/GTL/GTL+ driver
3.0 V to 3.6 V operation with 5 V tolerant LVTTL input
GTL input and output 3.6 V tolerant
V
ref
adjustable from 0.5 V to 0.5V
CC
Partial power-down permitted
Latch-up protection exceeds 100 mA per JESD78
ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per
JESD22-CC101
AEC-Q100 compliance available
Package offered: TSSOP24
3. Quick reference data
Table 1.
Symbol
C
i
C
io
Quick reference data
Parameter
input capacitance
input/output capacitance
Conditions
control inputs;
V
I
= 3.0 V or 0 V
A port; V
O
= 3.0 V or 0 V
B port; V
O
= V
TT
or 0 V
GTL; V
ref
= 0.8 V; V
TT
= 1.2 V
t
PLH
t
PHL
t
PLH
t
PHL
LOW to HIGH propagation delay
HIGH to LOW propagation delay
LOW to HIGH propagation delay
HIGH to LOW propagation delay
An to Bn; see
Figure 3
An to Bn; see
Figure 3
Bn to An; see
Figure 4
Bn to An; see
Figure 4
-
-
-
-
2.8
3.4
5.2
4.9
5
7
8
7
ns
ns
ns
ns
Min
-
-
-
Typ
2
4.6
3.4
Max
2.5
6
4.3
Unit
pF
pF
pF
NXP Semiconductors
GTL2018
8-bit LVTTL to GTL transceiver
4. Ordering information
Table 2.
Ordering information
T
amb
=
40
C to +85
C.
Type number
GTL2018PW
GTL2018PW/Q900
[1]
[1]
Topside mark
GTL2018PW
Package
Name
TSSOP24
Description
plastic thin shrink small outline package; 24 leads;
body width 4.4 mm
Version
SOT355-1
GTL2018PW/Q900 is AEC-Q100 compliant. Contact
i2c.support@nxp.com
for PPAP.
5. Functional diagram
GTL2018
&
B0
A0
&
B1
A1
&
B2
A2
&
B3
A3
&
B4
A4
&
B5
A5
&
B6
A6
&
B7
A7
002aab603
VREF
DIR
Fig 1.
GTL2018
Logic diagram of GTL2018
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 29 August 2011
2 of 16
NXP Semiconductors
GTL2018
8-bit LVTTL to GTL transceiver
6. Pinning information
6.1 Pinning
GND
B0
B1
B2
B3
VREF
GND
B4
B5
1
2
3
4
5
6
7
8
9
24 V
CC
23 A0
22 A1
21 A2
20 A3
GTL2018PW
GTL2018PW/Q900
19 GND
18 A4
17 A5
16 A6
15 A7
14 V
CC
13 DIR
B6 10
B7 11
GND 12
002aab604
Fig 2.
Pin configuration for TSSOP24
6.2 Pin description
Table 3.
Symbol
GND
B0
B1
B2
B3
B4
B5
B6
B7
VREF
DIR
V
CC
A7
A6
A5
A4
A3
A2
A1
A0
Pin description
Pin
1, 7, 12, 19
2
3
4
5
8
9
10
11
6
13
14, 24
15
16
17
18
20
21
22
23
GTL reference voltage
direction control input (LVTTL)
positive supply voltage
data inputs/outputs (A side, LVTTL)
Description
ground (0 V)
data inputs/outputs (B side, GTL)
GTL2018
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 29 August 2011
3 of 16
NXP Semiconductors
GTL2018
8-bit LVTTL to GTL transceiver
7. Functional description
Refer to
Figure 1 “Logic diagram of GTL2018”.
7.1 Function table
Table 4.
Function table
H = HIGH voltage level; L = LOW voltage level.
Input
DIR
H
L
Input/output
An (LVTTL)
input
An = Bn
Bn (GTL)
Bn = An
input
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
V
I
< 0 V
A port
B port
V
O
< 0 V
output in OFF or
HIGH state; A port
output in OFF or
HIGH state; B port
I
OL
I
OH
T
stg
[1]
[2]
[3]
[4]
Conditions
Min
0.5
-
0.5
[1]
0.5
[1]
-
0.5
[1]
0.5
[1]
[2]
[2]
[3]
[4]
Max
4.6
50
7.0
4.6
50
7.0
4.6
32
80
32
+150
Unit
V
mA
V
V
mA
V
V
mA
mA
mA
C
LOW-level output current
HIGH-level output current
storage temperature
A port
B port
A port
-
-
-
60
The input and output negative voltage ratings may be exceeded if the input and output clamp current
ratings are observed.
Current into any output in the LOW state.
Current into any output in the HIGH state.
The performance capability of a high-performance integrated circuit in conjunction with its thermal
environment can create junction temperatures which are detrimental to reliability. The maximum junction
temperature of this integrated circuit should not exceed 150
C.
GTL2018
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 29 August 2011
4 of 16
NXP Semiconductors
GTL2018
8-bit LVTTL to GTL transceiver
9. Recommended operating conditions
Table 6.
Symbol
V
CC
V
TT
Recommended operating conditions
[1]
Parameter
supply voltage
termination voltage
[2]
GTL
GTL
GTL+
V
ref
reference voltage
overall
GTL
GTL
GTL+
V
I
V
IH
V
IL
I
OH
I
OL
T
amb
[1]
[2]
[3]
Conditions
Min
3.0
0.85
1.14
1.35
0.5
0.5
0.76
0.87
0
[3]
Typ
-
0.9
1.2
1.5
2
⁄ V
3 TT
Max
3.6
0.95
1.26
1.65
0.5V
CC
0.63
0.84
1.10
3.6
5.5
-
-
V
ref
0.050
0.8
16
40
16
+85
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
mA
mA
mA
C
0.6
0.8
1.0
V
TT
3.3
-
-
-
-
-
-
-
-
input voltage
HIGH-level input
voltage
LOW-level input
voltage
HIGH-level output
current
LOW-level output
current
ambient temperature
B port
except B port
B port
except B port
B port
except B port
A port
B port
A port
operating in
free air
0
V
ref
+ 0.050
2
-
-
-
-
-
40
Unused inputs must be held HIGH or LOW to prevent them from floating.
V
TT
maximum of 3.6 V with resistor sized to so I
OL
maximum is not exceeded.
A0 to A7 V
I(max)
is 3.6 V if configured as outputs (DIR = LOW).
GTL2018
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 29 August 2011
5 of 16
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