Datasheet> 器件分类 > 可编程逻辑器件> 可编程逻辑> LFE2-12SE-6T144I

LFE2-12SE-6T144I: 产品描述FPGA - Field Programmable Gate Array 12K LUTs S-Ser 1.2V -6 Spd I; 产品类别可编程逻辑器件可编程逻辑; 文件大小16MB，共771页; 制造商Lattice(莱迪斯); 官网地址http://www.latticesemi.com

下载文档详细参数全文预览

LFE2-12SE-6T144I在线购买

供应商	器件名称	价格	最低购买	库存
	LFE2-12SE-6T144I	-	-	点击查看	点击购买

LFE2-12SE-6T144I概述

FPGA - Field Programmable Gate Array 12K LUTs S-Ser 1.2V -6 Spd I

LFE2-12SE-6T144I规格参数

参数名称	属性值
是否无铅	含铅
是否Rohs认证	不符合
厂商名称	Lattice(莱迪斯)
零件包装代码	QFP
包装说明	TQFP-144
针数	144
Reach Compliance Code	not_compliant
ECCN代码	EAR99
最大时钟频率	357 MHz
CLB-Max的组合延迟	0.331 ns
JESD-30 代码	S-PQFP-G144
JESD-609代码	e0
长度	20 mm
湿度敏感等级	3
输入次数	93
逻辑单元数量	12000
输出次数	93
端子数量	144
最高工作温度	85 °C
最低工作温度	-40 °C
封装主体材料	PLASTIC/EPOXY
封装代码	LFQFP
封装等效代码	QFP144,.87SQ,20
封装形状	SQUARE
封装形式	FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）	225
电源	1.2 V
可编程逻辑类型	FIELD PROGRAMMABLE GATE ARRAY
认证状态	Not Qualified
座面最大高度	1.6 mm
最大供电电压	1.26 V
最小供电电压	1.14 V
标称供电电压	1.2 V
表面贴装	YES
温度等级	INDUSTRIAL
端子面层	Tin/Lead (Sn85Pb15)
端子形式	GULL WING
端子节距	0.5 mm
端子位置	QUAD
处于峰值回流温度下的最长时间	30
宽度	20 mm

文档预览

下载PDF文档

全文
预览

LatticeECP2/M Family Handbook

HB1003 Version 05.3, February 2012

LatticeECP2/M Family Handbook

Table of Contents

February 2012

Section I. LatticeECP2/M Family Data Sheet

Introduction

Features ............................................................................................................................................................. 1-1

Introduction ........................................................................................................................................................ 1-2

Architecture

Architecture Overview ........................................................................................................................................ 2-1

PFU Blocks ........................................................................................................................................................ 2-3

Slice .......................................................................................................................................................... 2-3

Modes of Operation................................................................................................................................... 2-5

Routing............................................................................................................................................................... 2-6

sysCLOCK Phase Locked Loops (GPLL/SPLL) ................................................................................................ 2-6

General Purpose PLL (GPLL) ................................................................................................................... 2-6

Standard PLL (SPLL) ................................................................................................................................ 2-7

Delay Locked Loops (DLL)................................................................................................................................. 2-8

DLLDELA Delay Block .............................................................................................................................. 2-9

PLL/DLL Cascading .................................................................................................................................. 2-9

GPLL/SPLL/GDLL PIO Input Pin Connections (LatticeECP2M Family Only) .................................................. 2-10

Clock Dividers .................................................................................................................................................. 2-10

Clock Distribution Network ............................................................................................................................... 2-11

Primary Clock Sources............................................................................................................................ 2-11

Secondary Clock/Control Sources .......................................................................................................... 2-13

Edge Clock Sources................................................................................................................................ 2-14

Primary Clock Routing ............................................................................................................................ 2-15

Dynamic Clock Select (DCS) .................................................................................................................. 2-15

Secondary Clock/Control Routing ........................................................................................................... 2-15

Slice Clock Selection............................................................................................................................... 2-17

Edge Clock Routing ................................................................................................................................ 2-18

sysMEM Memory ............................................................................................................................................. 2-19

sysMEM Memory Block........................................................................................................................... 2-19

Bus Size Matching .................................................................................................................................. 2-19

RAM Initialization and ROM Operation ................................................................................................... 2-19

Memory Cascading ................................................................................................................................. 2-19

Single, Dual and Pseudo-Dual Port Modes............................................................................................. 2-19

Memory Core Reset ................................................................................................................................ 2-20

EBR Asynchronous Reset....................................................................................................................... 2-20

sysDSP™ Block ............................................................................................................................................... 2-21

sysDSP Block Approach Compared to General DSP ............................................................................. 2-21

sysDSP Block Capabilities ...................................................................................................................... 2-21

MULT sysDSP Element .......................................................................................................................... 2-23

MAC sysDSP Element ............................................................................................................................ 2-24

MULTADDSUB sysDSP Element ........................................................................................................... 2-25

MULTADDSUBSUM sysDSP Element ................................................................................................... 2-26

Clock, Clock Enable and Reset Resources ............................................................................................ 2-26

Signed and Unsigned with Different Widths............................................................................................ 2-27

OVERFLOW Flag from MAC .................................................................................................................. 2-27

IPexpress™............................................................................................................................................. 2-28

Optimized DSP Functions ................................................................................................................................ 2-28

Resources Available in the LatticeECP2/M Family ................................................................................. 2-28

or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

www.latticesemi.com

Lattice Semiconductor

Table of Contents

LatticeECP2/M Family Handbook

LatticeECP2/M DSP Performance .......................................................................................................... 2-29

Programmable I/O Cells (PIC) ......................................................................................................................... 2-29

PIO ................................................................................................................................................................... 2-31

Input Register Block ................................................................................................................................ 2-31

Output Register Block ............................................................................................................................. 2-33

Tristate Register Block ............................................................................................................................ 2-35

Control Logic Block ................................................................................................................................. 2-35

DDR Memory Support...................................................................................................................................... 2-35

Left and Right Edges............................................................................................................................... 2-35

Bottom Edge ........................................................................................................................................... 2-35

Top Edge................................................................................................................................................. 2-36

DLL Calibrated DQS Delay Block ........................................................................................................... 2-37

Polarity Control Logic .............................................................................................................................. 2-39

DQSXFER............................................................................................................................................... 2-40

sysI/O Buffer .................................................................................................................................................... 2-40

sysI/O Buffer Banks ................................................................................................................................ 2-40

Typical sysI/O I/O Behavior During Power-up......................................................................................... 2-43

Supported sysI/O Standards ................................................................................................................... 2-43

Hot Socketing.......................................................................................................................................... 2-45

SERDES and PCS (Physical Coding Sublayer)............................................................................................... 2-46

SERDES Block........................................................................................................................................ 2-46

PCS......................................................................................................................................................... 2-47

SCI (SERDES Client Interface) Bus........................................................................................................ 2-47

IEEE 1149.1-Compliant Boundary Scan Testability......................................................................................... 2-48

Device Configuration........................................................................................................................................ 2-48

Soft Error Detect (SED) Support ............................................................................................................. 2-48

External Resistor..................................................................................................................................... 2-49

On-Chip Oscillator................................................................................................................................... 2-49

Density Shifting ................................................................................................................................................ 2-49

DC and Switching Characteristics

Absolute Maximum Ratings

, ,

............................................................................................................................. 3-1

Recommended Operating Conditions ................................................................................................................ 3-1

Hot Socketing Specifications.............................................................................................................................. 3-2

ESD Performance .............................................................................................................................................. 3-2

DC Electrical Characteristics.............................................................................................................................. 3-3

LatticeECP2 Supply Current (Standby).............................................................................................................. 3-4

LatticeECP2M Supply Current (Standby)........................................................................................................... 3-5

LatticeECP2 Initialization Supply Current .......................................................................................................... 3-6

LatticeECP2M Initialization Supply Current ....................................................................................................... 3-7

SERDES Power Supply Requirements (LatticeECP2M Family Only) ............................................................... 3-8

SERDES Power (LatticeECP2M Family Only)................................................................................................... 3-8

sysI/O Recommended Operating Conditions..................................................................................................... 3-9

sysI/O Single-Ended DC Electrical Characteristics.......................................................................................... 3-10

sysI/O Differential Electrical Characteristics .................................................................................................... 3-11

LVDS....................................................................................................................................................... 3-11

Differential HSTL and SSTL.................................................................................................................... 3-11

LVDS25E ................................................................................................................................................ 3-12

LVCMOS33D .......................................................................................................................................... 3-12

BLVDS .................................................................................................................................................... 3-13

LVPECL .................................................................................................................................................. 3-14

RSDS ...................................................................................................................................................... 3-15

MLVDS.................................................................................................................................................... 3-16

Typical Building Block Function Performance.................................................................................................. 3-17

Pin-to-Pin Performance (LVCMOS25 12mA Drive) ................................................................................ 3-17

Lattice Semiconductor

Table of Contents

LatticeECP2/M Family Handbook

Register-to-Register Performance .......................................................................................................... 3-17

Derating Timing Tables .................................................................................................................................... 3-18

LatticeECP2/M External Switching Characteristics.......................................................................................... 3-19

LatticeECP2/M Internal Switching Characteristics ........................................................................................... 3-28

Timing Diagrams .............................................................................................................................................. 3-30

LatticeECP2/M Family Timing Adders ............................................................................................................. 3-32

sysCLOCK GPLL Timing ................................................................................................................................. 3-35

sysCLOCK SPLL Timing.................................................................................................................................. 3-36

DLL Timing....................................................................................................................................................... 3-37

SERDES High-Speed Data Transmitter (LatticeECP2M Family Only) ............................................................ 3-38

SERDES High Speed Data Receiver (LatticeECP2M Family Only) ................................................................ 3-41

Input Data Jitter Tolerance...................................................................................................................... 3-41

SERDES External Reference Clock (LatticeECP2M Family Only) ......................................................... 3-43

SERDES Power-Down/Power-Up Specification .............................................................................................. 3-43

PCI Express Electrical and Timing Characteristics .......................................................................................... 3-44

AC and DC Characteristics ..................................................................................................................... 3-44

LatticeECP2/M sysCONFIG Port Timing Specifications .................................................................................. 3-46

JTAG Port Timing Specifications ..................................................................................................................... 3-50

Switching Test Conditions................................................................................................................................ 3-51

Pinout Information

Signal Descriptions ............................................................................................................................................ 4-1

PICs and DDR Data (DQ) Pins Associated with the DDR Strobe (DQS) Pin .................................................... 4-4

LatticeECP2 Pin Information Summary, LFE2-6 and LFE2-12 .......................................................................... 4-5

LatticeECP2 Pin Information Summary, LFE2-20 and LFE2-35 ........................................................................ 4-7

LatticeECP2 Pin Information Summary, LFE2-50 and LFE2-70 ........................................................................ 4-9

LatticeECP2M Pin Information Summary, LFE2M20 and LFE2M35 ............................................................... 4-11

LatticeECP2M Pin Information Summary, LFE2M50, LFE2M70 and LFE2M100............................................ 4-13

Available Device Resources by Package, LatticeECP2................................................................................... 4-15

Available Device Resources by Package, LatticeECP2M................................................................................ 4-15

LatticeECP2 Power Supply and NC................................................................................................................. 4-16

LatticeECP2 Power Supply and NC (Cont.)..................................................................................................... 4-17

LatticeECP2M Power Supply and NC.............................................................................................................. 4-18

LatticeECP2M Power Supply and NC (Cont.).................................................................................................. 4-19

LatticeECP2M Power Supply and NC (Cont.).................................................................................................. 4-21

LFE2-6E/SE and LFE2-12E/SE Logic Signal Connections: 144 TQFP ........................................................... 4-22

LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 208 PQFP......................................................... 4-26

LFE2-6E/SE and LFE2-12E/SE Logic Signal Connections: 256 fpBGA .......................................................... 4-31

LFE2-20E/SE Logic Signal Connections: 256 fpBGA ...................................................................................... 4-39

LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 484 fpBGA ........................................................ 4-47

LFE2-35E/SE and LFE2-50E/SE Logic Signal Connections: 484 fpBGA ........................................................ 4-60

LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA ........................................................ 4-73

LFE2-50E/SE and LFE2-70E/SE Logic Signal Connections: 672 fpBGA ........................................................ 4-91

LFE2-70E/SE Logic Signal Connections: 900 fpBGA .................................................................................... 4-109

LFE2M-20E/SE and LFE2M-35E/SE Logic Signal Connections: 256 fpBGA ................................................ 4-134

LFE2M20E/SE and LFE2M35E/SE Logic Signal Connections: 484 fpBGA .................................................. 4-141

LFE2M50E/SE Logic Signal Connections: 484 fpBGA .................................................................................. 4-153

LFE2M35E/SE and LFE2M50E/SE Logic Signal Connections: 672 fpBGA .................................................. 4-167

LFE2M50E/SE and LFE2M70E/SE Logic Signal Connections: 900 fpBGA .................................................. 4-184

LFE2M100E/SE Logic Signal Connections: 900 fpBGA ................................................................................ 4-206

LFE2M70E/SE and LFE2M100E/SE Logic Signal Connections: 1152 fpBGA .............................................. 4-231

Ordering Information

LatticeECP2 Part Number Description............................................................................................................... 5-1

Ordering Information .......................................................................................................................................... 5-1

LatticeECP2 Standard Series Devices, Conventional Packaging............................................................. 5-2

Lattice Semiconductor

Table of Contents

LatticeECP2/M Family Handbook

LatticeECP2 Standard Series Devices, Lead-Free Packaging .......................................................................... 5-5

LatticeECP2 S-Series Devices, Conventional Packaging......................................................................... 5-8

LatticeECP2 S-Series Devices, Lead-Free Packaging ........................................................................... 5-11

LatticeECP2M Part Number Description.......................................................................................................... 5-14

Ordering Information ........................................................................................................................................ 5-14

LatticeECP2M Standard Series Devices, Conventional Packaging........................................................ 5-15

LatticeECP2M Standard Series Devices, Lead-Free Packaging ............................................................ 5-18

LatticeECP2M S-Series Devices, Lead-Free Packaging ........................................................................ 5-23

Supplemental Information

For Further Information ...................................................................................................................................... 6-1

LatticeECP2/M Family Data Sheet Revision History

Revision History ................................................................................................................................................. 7-1

Section II. LatticeECP2/M Family Technical Notes

LatticeECP2M SERDES/PCS Usage Guide

Introduction to PCS ............................................................................................................................................ 8-1

Features ............................................................................................................................................................. 8-1

Supported Standards ......................................................................................................................................... 8-2

Architecture Overview ........................................................................................................................................ 8-2

PCS Quad ................................................................................................................................................. 8-2

PCS Quad and Channels.......................................................................................................................... 8-3

Per Channel PCS/FPGA Interface Ports................................................................................................... 8-4

Locating a PCS Quad ............................................................................................................................... 8-4

Detailed Channel Block Diagram .............................................................................................................. 8-4

SCI (SERDES Client Interface) Bus.......................................................................................................... 8-7

Using This Technical Note ........................................................................................................................ 8-7

SERDES/PCS .................................................................................................................................................... 8-7

I/O Definitions............................................................................................................................................ 8-9

SERDES/PCS Functional Description ............................................................................................................. 8-12

SERDES ................................................................................................................................................. 8-12

Reference Clock Usage .......................................................................................................................... 8-13

Transmit Data.......................................................................................................................................... 8-16

Receive Data........................................................................................................................................... 8-16

Configuration GUIs........................................................................................................................................... 8-27

Configuration File Description ................................................................................................................. 8-38

LatticeECP2M PCS in Gigabit Ethernet Mode ................................................................................................. 8-39

Gigabit Ethernet (1000BASE-X) Idle Insert............................................................................................. 8-39

Gigabit Ethernet Idle Insert and ff_correct_disp_ch[3:0] Signal Usage................................................... 8-39

LatticeECP2M PCS in PCI Express Mode ....................................................................................................... 8-39

PCS Loopback Modes ..................................................................................................................................... 8-41

Serial Loopback Mode ............................................................................................................................ 8-41

SERDES Parallel Loopback Mode.......................................................................................................... 8-41

PCS Parallel Loopback Mode ................................................................................................................. 8-41

FPGA Interface Clocks Usage ......................................................................................................................... 8-42

2-to-1 Gearing ......................................................................................................................................... 8-44

SERDES/PCS Block Latency........................................................................................................................... 8-49

SERDES Client Interface (SCI)........................................................................................................................ 8-50

Interrupts and Status............................................................................................................................... 8-52

SERDES Client Interface Application Example....................................................................................... 8-53

Dynamic Configuration of SERDES/PCS Quad...................................................................................... 8-54

SERDES Debug Capabilities .................................................................................................................. 8-54

Control Boxes and Buttons, Status Boxes and the Text Window ........................................................... 8-56

Other Design Considerations ........................................................................................................................... 8-56

LatticeECP2M-35 vs. All Other LatticeECP2M Devices.......................................................................... 8-56

推荐资源

HT-6010／6012／6013／6014／6015电路-a

恒流源与电流反馈的入门概念: 所谓恒压源就是输出电压“极其稳定”，不随负载变化。为了保证电压不变，输出电流必须始终符合I=V/R。即负载R需要多大电流，恒压源就必须输出多大电流，“无条件”予以满足。从外部看，就是输出 ......; fighting 电源技术

单片机C语言程序设计实训100例: 单片机C语言程序设计实训100例...; backhuli 单片机

【关注】《ARM嵌入式常用模块与综合系统设计实例精讲》练习题与答案: 本文转引自广告,被过滤 ARM技术讨论版广告,被过滤非常详细的问题集锦，相信朋友们看过之后会对整个嵌入式ARM有一个更高远更深刻的认识。第1章：填空题 1．ARM内核有四个功能模块 ......; qdjxll ARM技术

谁用过SIM908？: SIM908的电路怎么连接？和STM32连接是不是连接GPS/DBUG-TXD 、GPS/DBUG-RXD和TXD、RXD这四个引脚就可以了？然后SIM908连接SIM卡和PWRKEY?主要的是不是这些就够了，有没有电路啊，交流下 ...; 玻璃之城2046 stm32/stm8

有个问题没搞明白哈: 50148 4096位置有同样的寄存器，干嘛用那么多，请各位看官评评理，这不是巨大的浪费么？...; ddllxxrr NXP MCU

超声宽景成像技术介绍: 宽景成像技术是利用常规扫查探头生成宽景图像的过程。常规的超声探头扫查诊断时，医生可实时观察到探头所在体表切面的图像，然后通过不断地移动探头，观察周围较大器官的组织结构，并选择保 ......; banana 医疗电子

STM32F4 编程手册学习1_编程模型

1. 处理器模式与特权等级处理器模式分为以下两种：线程模式：用来执行应用软件；处理器从reset出来时，进入线程模式； CONTROL寄存器控制软件的执行状态时特权的还是非特权的。处理模式：用来处理异常；完成异常处理后，进入线程模式；该模式下，软件运行在特权等级上。特权等级有以下两种：非特权：对于MSR、MRS指令受限的权限，不能使用CPS指令；不能使用系统定时器...[详细]
STM32时钟系统之利用 systick 定时器来实现准确的延时

　　本篇文章带着大家来认识一下 STM32 的时钟系统，以及利用 systick 定时器来实现一个比较准确的延时。　　我们首先从时钟说起，时钟在MCU中的作用，就好比于人类的心脏一样不可或缺。STM32 的时钟相比 51 的单一时钟要复杂些，它有多个时钟源可以使用，那么大家可能会有所疑惑，STM32 的时钟搞的那么复杂干什么，原因其实在于，STM32的外设资源比起51来说，是很丰富的，那么不同...[详细]
450Wh/kg！融捷集团发布第二代硫化物全固态电池

当固态电池行业仍在为电动汽车的“终极方案”进行漫长的技术马拉松时，部分企业已开始寻找更切近的商业化落地场景。近日，融捷集团旗下的融捷能源科技有限公司（以下简称“融捷能源”）正式推出其第二代全固态硫化物电池，能量密度达到450 Wh/kg。固态电池迈向实处，三赛道精准卡位 2025年，全球固态电池产业进入了一个关键的“去芜存菁”阶段。在经历多轮资本与产业的热潮起伏后，市场正...[详细]
基于单片机的FLAC高保真数字音频播放器设计

一、项目概述 1.1 引言目前，大部分的音乐文件都是以mp3格式来保存的，mp3是一种有损的音频压缩格式，它无法完美地再现原版音乐。随着存储器容量的扩大、网络带宽的增加、处理器性能的增强以及人们对生活品质要求的提高，无损音乐越来越受到人们的青睐，对无损音乐播放器的需求也就越来越大。 1.2 项目背景/选题动机我们希望能在 AVR 单片机上实现一个“FLAC高保真音频播放器”。播放器用...[详细]
纯电动汽车智能供电系统对我们生活的影响

纯电动汽车作为新能源汽车中的主推车型，近年来得到了国家的大力支持与鼓励，发展也是日新月异，对于纯电动汽车在我们之前的认知，它是一个需要进行充电才能够提供动力输出的一个庞大的耗电体，而在近期发布的车型不知道大家有没有发现，不管是北汽EX5、还是最新发布的几何A都增加了对外放电功能，纯电动汽车摇身一变成为了可充放电的智能移动终端，今天小编就带大家一起纯电动汽车的对外放电功能，看看它究竟会为我们带来哪...[详细]
应用案例 | 当机械臂抓取物料时，如何精准拿捏尺度？

随着工业自动化行业的不断发展，可以看到越来越多的智能设备采用灵活、高效、精准的机械臂完成定位抓取、组装等。最常见的是使用机器视觉应用，机器视觉将目标物体的图像信息通过光学设备和传感器获取后，将其转化为数字化信息（坐标位置和角度），并依据控制单元指导，使机器可以有效地执行任务。但这次的任务中，我们选择了更经济的激光位移测距方案来实现机械臂的定位抓取，本期小明就来分享一下具体的应用情况~...[详细]
麦格纳推出集成式舱内感知系统：将摄像头与雷达融合用于舱内主动安全

麦格纳推出的集成式舱内感知系统将视觉与毫米波雷达数据融合，用于检测乘员存在、识别儿童滞留、监测驾驶员疲劳及生命体征，支持无接触安全带检测等功能。图片来源：麦格纳该系统通过多模态验证提升检测鲁棒性，可直接响应法规要求（例如儿童滞留报警）并与车载HVAC、座椅和安全控制单元联动，实现出车前的自动巡检与离车提醒。该类集成方案特别适配家庭化MPV、带自动驾驶功能的大型商用车以及共享出行业务...[详细]
MODBUS转PROFIBUS网关YT-PB-03将仪表接入PROFIBUS的配制方法

工具/原料移通创联MODBUS转PROFIBUS网关YT-PB-03 西门子s7-300 本文主要介绍MODBUS转PROFIBUS网关YT-PB-03将仪表接入PROFIBUS的配制方法。移通创联MODBUS转PROFIBUS网关YT-PB-03广泛应用于变频器、电机启动保护装置、智能高低压电器、电量测量装置、各种变送器、智能现场测量设备及仪表等等,都可以使用该rs485转PROF...[详细]
纳芯微推出三款用于 GaN、汽车和电池安全的芯片

纳芯微正在推出涵盖各种电源应用的器件，包括氮化镓 (GaN) 驱动器、双通道汽车驱动器和电池保护 MOSFET。随着各行各业的电源系统日益紧凑和复杂，工程师们不得不重新思考如何在高压、汽车和电池供电设计中管理效率、控制和保护。氮化镓技术有望实现更高的功率密度，汽车电子设备需要具有严格 EMC 限制的多电机控制，而锂电池系统的能量和电流需求也在迅速增长。挑战在于找到既能满足这些需求，又不会增...[详细]
三相电开水器的工作原理及接法

　　热水器的组成　　热水器本身总共分为以下部分：　　1.水箱。　　这是热水器的装水的地方，是我们用水的加工场所。　　2.加热管　　热水器的里面，有三根连在一起的像是热得快一样的东西，这就是我们的加热装置，也是最容易坏的东西。如果它坏了的话，那么就直接把它卸下来，然后换一个新的安上去就可以了。具体拆卸方法见下文。　　　　3.交流接触器　　　　交流接触器就是一个开关...[详细]
电动汽车的电池养护需要注意哪些方面的细节

电池作为电动汽车的核心，关心车辆的用车和养车等，而车辆的运行都是靠电池所产生电能来保证的，对于电池而言电池的使用和养护来说就是很重要的一个环节了，对于电动汽车来说，电动汽车电池养护需要注意哪些细节？首先对于车辆来说，定期的按照要求对电池进行检查和保养，使用的时候避免过渡电池出现过渡放电现象，在行车的时候保持良好的驾驶习惯，尽量避免猛踩加速，对于电池而言，猛加速会使得电池内部的电极之间形成瞬...[详细]
在选择电动汽车时需要注意哪方面的细节

纯电动汽车，在近几年来有着极其迅猛的发展，至如今，不少消费者在选车买车时，都会将纯电动车型列入到自己的备选名单中。但你知道怎么选购一款满意且安全的纯电动汽车吗？什么样的纯电动汽车最值得选购？文章里告诉你答案。机械素质是许多消费者选择纯电动汽车所关注的第一要素，这其中包含有充电时长、充电功率、电动机输出功率以及至为重要的续航里程等。在这一系列的因素里，续航里程是需要着重关注的一个，续航里程的...[详细]
EVD系列电子膨胀阀控制模块详解

我们先来看一下EVD系列的开发理念。 EVD控制模块是专门为工作在极端环境下而开发的，选用符合极端环境下要求的元器件，选用硅胶和树脂全密封，也就是说，我们的控制模块内层使用硅胶填充，保证元器件的电气性能，外层使用树脂全密封，保证控制模块的密封性。从而使EVD控制模块，适合安装在冷库这种低温潮湿的环境当中。我们再看下一EVD系列的测试环境。 EVD控制模块在极端的温湿度环境下持续测试三个月...[详细]
新能源电动汽车的缺点主要体现在哪些方面

新能源电动汽车节能，环保，用车成本低，以及享受国家政策的大力支持，随着新能源电动汽车的销售增长，对于新能源电动汽车的选择上面来说，也吸引了越来越多的人选择，从新能源电动汽车优点上面来说，占有的优点有很多，但电动汽车有优点也就有缺点。从电动汽车的缺点上面来说，首先车辆的充电速度慢，对于电动汽车来说，虽然有快充和慢充，但是从快充的角度上面而言，并不能像燃油车加油那样的快，一般正常的充电时间为8...[详细]
对于家用汽车而言是选择纯电动好还是燃油好

好于不好不能一概而论，所处环境不一样，“好的”定义也不一样。排除政策扶植后，电动汽车好还是燃油汽车好，要从自己的实际用车需求与使用环境做出选择。首先就是续航里程，电动车续航里程与很多因素有关系。厂商标注的续航里程只是等速续航里程，实际使用中是要大打折扣的。北方地区进入冬季后，环境温度在-10℃以下，极寒地区最低温度达到-30℃。这样的环境温度，电动车的锂电池会受到影响，锂离子活性降低、放电...[详细]

器件捷径: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

热门器件

开源项目推荐更多

热门活动更多

热门文章更多

技术资料推荐更多