FemtoClock® NG
Crystal-to-LVCMOS/LVTTL Clock
840N021
DATA SHEET
General Description
The 840N021 is a LVCMOS/LVTTL clock synthesizer designed for
Ethernet applications. The device generates a 125MHz clock signal
from a 25MHz crystal with excellent phase jitter performance. The
device uses IDT’s fourth generation FemtoClock
®
NG technology for
an optimum of high clock frequency, low phase noise performance
and low power consumption.The device supports 2.5V or 3.3V
voltage supply and is packaged in a small, lead-free (RoHS 6) 8-lead
TSSOP package. The extended temperature range supports
wireless infrastructure, telecommunication and networking end
equipment requirements. The device is a member of the
high-performance clock family from IDT.
Features
•
•
•
•
•
•
•
•
•
•
•
Fourth generation FemtoClock
®
NG technology
125MHz output clock synthesized from a 25MHz fundamental
mode crystal
One 2.5V or 3.3V LVCMOS/LVTTL clock output
Crystal interface designed for a 12pF parallel resonant crystal
RMS phase jitter @ 125MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.156ps (maximum)
RMS phase jitter @ 100MHz, using a 20MHz crystal
(12kHz - 20MHz): 0.451ps (maximum)
LVCMOS interface level for the output enable input
Full 2.5V or 3.3V supply voltage
Lead-free (RoHS 6) packaging
-40°C to 85°C ambient operating temperature
Use replacement part 840N202CKI-dddLF
Frequency Table
f
XTAL
(MHz)
20
25
Q Output Frequency (MHz)
100
125
Function Table
Input
OE
0
1 (default)
Output Enable
Output Q is disabled in high-impedance state
Output Q is enabled.
NOTE: OE is an asynchronous control.
Block Diagram
XTAL_IN
OSC
XTAL_OUT
PFD
&
LPF
FemtoClock NG
VCO
490-637.5MHz
®
Pin Assignment
÷5
Q
VDDA
OE
XTAL_OUT
XTAL_IN
1
2
3
8
7
6
5
VDD
Q
GND
DNU
4
OE
Pullup
÷25
840N021
8-lead TSSOP
4.40mm x 3.0mm x 0.925mm
package body
G Package
Top View
840N021 REVISION A 8/14/15
1
©2015 Integrated Device Technology, Inc.
840N021 DATA SHEET
Pin Descriptions and Characteristics
Table 1. Pin Descriptions
Number
1
2
3,
4
5
6
7
8
Name
V
DDA
OE
XTAL_OUT,
XTAL_IN
DNU
GND
Q
V
DD
Power
Output
Power
Power
Input
Input
Pullup
Type
Description
Analog power supply.
Output enable pin. LVCMOS interface levels.
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
Do not use. Do not connect.
Power supply ground.
Single-ended clock output. LVCMOS/LVTTL interface levels.
Core supply pin.
NOTE:
Pullup
refers to an internal input resistor. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
C
PD
R
PULLUP
R
OUT
Parameter
Input Capacitance
Power Dissipation
Capacitance
Input Pullup Resistor
Output Impedance
V
DD
= 3.3V
V
DD
= 2.5V
Test Conditions
OE
V
DD
= 3.465V
V
DD
= 2.625V
Minimum
Typical
3.5
11
9
51
15
19
Maximum
Units
pF
pF
pF
k
REVISION A 8/14/15
2
FEMTOCLOCK® NG CRYSTAL-TO-LVCMOS/LVTTL CLOCK
SYNTHESIZER
840N021 DATA SHEET
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics or AC
Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
XTAL_IN
Other Inputs
Outputs, V
O
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
3.63V
0V to 2V
-0.5V to V
DD
+ 0.5V
-0.5V to V
DD
+ 0.5V
117°C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 3A. Power Supply DC Characteristics,
V
DD
= 3.3V±5% or 2.5V±5%, T
A
= -40°C to 85°C
Symbol
V
DD
V
DDA
V
DDA
I
DDA
I
DD
Parameter
Core Supply Voltage
Analog Supply Voltage
Analog Supply Voltage
Analog Supply Current
Power Supply Current
Test Conditions
Minimum
2.375
V
DD
– 0.18
V
DD
– 0.18
Typical
3.3
3.3
2.5
Maximum
3.465
V
DD
V
DD
18
67
Units
V
V
V
mA
mA
Table 3B. LVCMOS/LVTTL DC Characteristics,
V
DD
= 3.3V±5% or 2.5V±5%, T
A
= -40°C to 85°C
Symbol
V
IH
V
IL
I
IH
I
IL
V
OH
V
OL
Parameter
Input High Voltage
Test Conditions
V
DD
= 3.3V
V
DD
= 2.5V
V
DD
= 3.3V
V
DD
= 2.5V
OE
OE
Q
V
DD
= V
IN
= 3.465V or 2.625V
V
DD
= 3.465V or 2.625V,
V
IN
= 0V
V
DD
= 3.465V
V
DD
= 2.625V
V
DD
= 3.465V or 2.625V
-150
2.6
1.8
0.5
Minimum
2
1.7
-0.3
-0.3
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
0.7
5
Units
V
V
V
V
μA
μA
V
V
V
Input Low Voltage
Input High Current
Input Low Current
Output High
Voltage; NOTE 1
Output Low Voltage;
Q
NOTE 1
NOTE 1: Output terminated with 50 to V
DD
/ 2. See Parameter Measurement Information Section,
LVCMOS Output Load Test Circuit Diagrams.
FEMTOCLOCK® NG CRYSTAL-TO-LVCMOS/LVTTL CLOCK
SYNTHESIZER
3
REVISION A 8/14/15
840N021 DATA SHEET
Table 4. Crystal Characteristics
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Capacitive Load (C
L
)
12
19.6
Test Conditions
Minimum
Typical
Fundamental
25
25.5
80
7
MHz
pF
pF
Maximum
Units
AC Characteristics
Table 5. AC Characteristics,
V
DD
= 3.3V±5% or 2.5V±5%, T
A
= -40°C to 85°C
Symbol
f
OUT
Parameter
Output Frequency
RMS Phase Jitter (Random);
NOTE 1
f
OUT
= 125MHz, Integration Range:
1.875MHz – 20MHz, 25MHz crystal
f
OUT
= 100MHz, Integration Range:
12kHz – 20MHz, 20MHz crystal
f
OUT
= 125MHz, Offset: 10Hz
f
OUT
= 125MHz, Offset: 100Hz
f
OUT
= 125MHz, Offset: 1kHz
N
Single-Side Band Noise Power
f
OUT
= 125MHz, Offset: 10kHz
f
OUT
= 125MHz, Offset: 100kHz
f
OUT
= 125MHz, Offset: 1MHz
f
OUT
= 125MHz, Offset: 10MHz
t
R
/ t
F
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
200
48
Test Conditions
Minimum
98
Typical
125
0.111
0.348
-53.9
-83.8
-111.4
-128.4
-131.9
-141.3
-157.6
600
52
Maximum
127.5
0.156
0.451
Units
MHz
ps
ps
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
ps
%
tjit(Ø)
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE: Characterized with 20MHz and 25MHz crystals.
NOTE 1: Please refer to the phase noise plots.
REVISION A 8/14/15
4
FEMTOCLOCK® NG CRYSTAL-TO-LVCMOS/LVTTL CLOCK
SYNTHESIZER
840N021 DATA SHEET
Typical Phase Noise at 125MHz
Noise Power (dBc/Hz)
Offset Frequency (Hz)
Typical Phase Noise at 100MHz
Noise Power (dBc/Hz)
Offset Frequency (Hz)
FEMTOCLOCK® NG CRYSTAL-TO-LVCMOS/LVTTL CLOCK
SYNTHESIZER
5
REVISION A 8/14/15
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