NBSG72A
2.5V/3.3V SiGe Differential
2 x 2 Crosspoint Switch
with Output Level Select
The NBSG72A is a high−bandwidth fully differential 2 X 2
crosspoint switch with Output Level Select (OLS) capabilities. This is
a part of the GigaComm™ family of high performance Silicon
Germanium products. The device is housed in a low profile 3 X 3 mm
16−pin QFN package.
Differential inputs incorporate internal 50
W
termination resistors
and accept NECL (Negative ECL), PECL (Positive ECL),
LVCMOS/LVTTL, CML, or LVDS. The OLS input is used to
program the peak−to−peak output amplitude between 0 mV and
800 mV in five discrete steps. The SELECT inputs are single−ended
and can be driven with either LVECL or LVCMOS/LVTTL
input levels.
Features
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MARKING
DIAGRAM*
1
1
QFN−16
MN SUFFIX
CASE 485G
•
•
•
•
•
Maximum Input Clock Frequency > 7 GHz Typical
Maximum Input Data Rate > 7 Gb/s Typical
200 ps Typical Propagation Delay (OLS = FLOAT)
55/45 ps Typical Rise/Fall Times (OLS = FLOAT)
Selectable Swing PECL Output with Operating Range:
V
CC
= 2.375 V to 3.465 V with V
EE
= 0 V
•
Selectable Swing NECL Output with NECL Inputs with
Operating Range: V
CC
= 0 V with V
EE
=
−2.375
V to
−3.465
V
•
Selectable Output Levels (0 mV, 200 mV, 400 mV, 600 mV or
800 mV Peak−to−Peak Output)
•
50
W
Internal Input Termination Resistors
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 13 of this data sheet.
•
Single−Ended LVECL or LVCMOS/LVTTL Select Inputs
(SELA, SELB)
•
Pb−Free Packages are Available
©
Semiconductor Components Industries, LLC, 2010
November, 2010
−
Rev. 7
1
Publication Order Number:
NBSG72A/D
ÇÇ
ÇÇ
16
SG
72A
ALYWG
G
NBSG72A
V
CC
16
V
TD0
D0
D0
SELA
1
2
NBSG72A
3
4
5
V
EE
6
D1
7
D1
8
V
TD1
Q0
15
Q0
14
OLS
13
12 V
CC
11 Q1
10 Q1
9
SELB
Exposed Pad (EP)
Figure 1. QFN−16 Pinout
(Top View)
Table 1. PIN DESCRIPTION
Pin No.
1
2
Name
VTD0
D0
I/O
−
LVDS, CML, ECL,
LVTTL, LVCMOS
Input
LVDS, CML, ECL,
LVTTL, LVCMOS
Input
LVECL, LVCMOS
Input
−
LVDS, CML, ECL,
LVTTL, LVCMOS
Input
LVDS, CML, ECL,
LVTTL, LVCMOS
Input
−
LVECL, LVCMOS
Input
RSECL Output
RSECL Output
−
Input
RSECL Output
RSECL Output
−
−
Inverted Differential Input 0.
Description
Common Internal 50
W
Termination Pin for D0 and D0 Input. See Table 4. (Note 1)
3
D0
Noninverted Differential Input 0.
4
5
6
SELA
V
EE
D1
Select Logic Input A. Internal 75 kW Pulldown to V
EE
.
Negative Supply. All V
EE
Pins must be Externally Connected to Power Supply to
Guarantee Proper Operation.
Inverted Differential Input 1.
7
D1
8
9
VTD1
SELB
Q1
Q1
10
11
12
13
14
15
16
−
V
CC
OLS
(Note 2)
Q0
Q0
V
CC
EP
1. In the differential configuration when the input termination pins (VTD0, VTD1) are connected to a common termination voltage, and if no signal
is applied then the device will be susceptible to self−oscillation.
2. When an output level of 400 mV is desired and V
CC
−
V
EE
> 3.0 V, 2 kW resistor should be connected from OLS pin to V
EE
.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
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ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Noninverted Differential Input 1.
Common Internal 50
W
Termination Pin for D1 and D1 Input. See Table 4. (Note 1)
Select Logic Input B. Internal 75 kW Pulldown to V
EE
.
Noninverted Differential Output.
Inverted Differential Output.
Positive Supply. All V
CC
Pins must be Externally Connected to Power Supply to
Guarantee Proper Operation.
Input Pin for Output Level Select (OLS) See Table 3.
Noninverted Differential Output Typically Terminated with 50
W
Resistor to
V
TT
= V
CC
−
2.0 V.
Inverted Differential Output Typically Terminated with 50
W
Resistor to
V
TT
= V
CC
−
2.0 V.
Positive Supply. All V
CC
Pins must be Externally Connected to Power Supply to
Guarantee Proper Operation.
The Exposed Pad (EP) and the QFN−16 package bottom is thermally connected to
the die for improved heat transfer out of package. The exposed pad must be attached
to a heat−sinking conduit. The pad is not electrically connected to the die but may be
electrically and thermally connected to V
EE
on the PC board.
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Á
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2
NBSG72A
VTD0
D0
D0
D1
D1
50
W
VTD1
SELA
75 kW
2
SELB
75 kW
OLS
2
50
W
2
2
2
Q1
Q1
V
CC
V
EE
2
2
50
W
50
W
2
2
2
Q0
Q0
+
Table 2. TRUTH TABLE
SELA
LOW
HIGH
LOW
HIGH
SELB
LOW
LOW
HIGH
HIGH
Q0
D0
D1
D0
D1
Q1
D0
D0
D1
D1
Figure 2. Logic/Block Diagram
Table 3. OUTPUT LEVEL SELECT (OLS)
OLS
V
CC
V
CC
−
0.4 V
V
CC
−
0.8 V
V
CC
−
1.2 V
V
EE
(Note 3)
FLOAT
Output Amplitude (V
OUTPP
)
800 mV
200 mV
600 mV
0
400 mV
600 mV
OLS Sensitivity
OLS
−
75 mV
OLS
±
150 mV
OLS
±
100 mV
OLS
±
75 mV
OLS
±
100 mV
N/A
3. When an output level of 400 mV is desired and V
CC
−
V
EE
> 3.0 V, a 2 kW resistor should be connected from OLS to V
EE
.
Table 4. INTERFACING OPTIONS
Interfacing Options
CML
LVDS
AC−COUPLED
RSECL, PECL, NECL
LVCMOS / LVTTL
Connect VTD0 and VTD1 to V
CC
VTD0 and VTD1 Should Be Left Floating.
Bias VTD0 and VTD1 Inputs within Common Mode Range (VIHCMR)
Standard ECL Termination Techniques
The external voltage should be applied to the unused complementary differential input.
Nominal voltage is 1.5 V for LVTTL and V
CC
/2 for LVCMOS Inputs.
Connections
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3
NBSG72A
Table 5. ATTRIBUTES
Characteristics
Internal Input Pulldown Resistor (SELA, SELB)
ESD Protection
Human Body Model
Machine Model
Charged Device Model
Value
75 kW
> 2 kV
> 50 V
> 1 kV
Level 1
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
436
Moisture Sensitivity (Note 1)
Flammability Rating
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 6. MAXIMUM RATINGS
Symbol
V
CC
V
EE
V
I
V
INPP
I
out
I
IN
T
A
T
stg
q
JA
q
JC
T
sol
Parameter
Positive Power Supply
Negative Power Supply
Positive Input
Negative Input
Differential Input Voltage |D
X
−
D
X
|
Output Current
Input Current Through R
T
(50
W
Resistor)
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient)
(Note 2)
Thermal Resistance (Junction−to−Case)
Wave Solder
Pb
Pb−Free
0 lfpm
500 lfpm
(Note 2)
< 3 sec @ 260°C
< 3 sec @ 260°C
QFN−16
QFN−16
QFN−16
Condition 1
V
EE
= 0 V
V
CC
= 0 V
V
EE
= 0 V
V
CC
= 0 V
V
EE
−
V
CC
w
2.8 V
V
EE
−
V
CC
t
2.8 V
Continuous
Surge
Static
Surge
V
I
V
CC
V
I
V
EE
Condition 2
Rating
3.6
−3.6
3.6
−3.6
2.8
|V
CC
−
V
EE
|
25
50
45
80
−40
to +85
−65
to +150
42
35
4
265
265
Units
V
V
V
V
V
mA
mA
mA
mA
°C
°C
°C/W
°C/W
°C/W
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2. JEDEC standard multilayer board
−
1S2P (1 signal, 2 power).
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NBSG72A
Table 7. DC CHARACTERISTICS, INPUT WITH PECL OUTPUT
V
CC
= 2.5 V; V
EE
= 0 V (Note 3)
−40°C
Symbol
I
EE
V
OH
V
OL
Characteristic
Negative Power Supply Current
Output HIGH Voltage (Note 4)
Output LOW Voltage (Note 4)
(OLS = V
CC
)
(OLS = V
CC
−
0.4 V)
(OLS = V
CC
−
0.8 V, OLS = FLOAT)
(OLS = V
CC
−
1.2 V)
(OLS = V
EE
)
Output Voltage Amplitude
(OLS = V
CC
)
(OLS = V
CC
−
0.4 V)
(OLS = V
CC
−
0.8 V, OLS = FLOAT)
(OLS = V
CC
−
1.2 V)
(OLS = V
EE
)
Input HIGH Voltage (Single−Ended)
(Note 6)
D0, D0, D1, D1, SELA, SELB
Input LOW Voltage (Single−Ended)
(Note 7)
D0, D0, D1, D1, SELA, SELB
Input HIGH Voltage Common Mode
Range (Differential Configuration) (Note 5)
Internal Input Termination Resistor
Input HIGH Current (@V
IH
)
Input LOW Current (@V
IL
)
670
125
510
0
325
V
EE
+
1275
V
EE
1.2
45
50
35
20
800
215
615
5
415
V
CC
−
1000*
V
CC
−
1400*
V
CC
V
IH
−
150
2.5
55
100
100
660
120
505
0
320
V
EE
+
1275
V
EE
1.2
45
50
35
20
795
210
610
0
410
V
CC
−
1000*
V
CC
−
1400*
V
CC
V
IH
−
150
2.5
55
100
100
655
120
500
0
320
V
EE
+
1275
V
EE
1.2
45
50
35
20
790
210
605
5
410
V
CC
−
1000*
V
CC
−
1400*
V
CC
V
IH
−
150
2.5
55
100
100
mV
mV
V
W
mA
mA
555
1235
775
1455
1005
705
1295
895
1505
1095
855
1385
1015
1585
1215
595
1270
810
1490
1040
745
1330
930
1540
1130
895
1420
1050
1620
1250
625
1295
840
1510
1065
775
1355
960
1560
1155
925
1445
1080
1640
1275
mV
Min
40
1460
Typ
55
1510
Max
65
1560
Min
40
1490
25°C
Typ
55
1540
Max
65
1590
Min
40
1515
85°C
Typ
55
1565
Max
65
1615
Unit
mA
mV
mV
V
OUTPP
V
IH
V
IL
V
IHCMR
R
TIN
I
IH
I
IL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
*Typicals used for testing purposes.
3. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary +0.125 V to
−0.965
V.
4. All loading with 50
W
to V
CC
−
2.0 V.
5. V
IHCMR
min varies 1:1 with V
EE
, V
IHCMR
max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential
input signal.
6. V
IH
cannot exceed V
CC
.
7. V
IL
always
w
V
EE
.
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