NBSG86A
2.5V/3.3V SiGe Differential
Smart Gate with Output
Level Select
The NBSG86A is a multi−function differential Logic Gate which
can be configured as an AND/NAND, OR/NOR, XOR/XNOR, or 2:1
MUX. This device is part of the GigaComm™ family of high
performance Silicon Germanium products. The device is housed in a
3 x 3 mm 16 pin QFN package.
Differential inputs incorporate internal 50
W
termination resistors
and accept NECL (Negative ECL), PECL (Positive ECL),
LVCMOS/LVTTL, CML, or LVDS. The Output Level Select (OLS)
input is used to program the peak−to−peak output amplitude between
0 and 800 mV in five discrete steps.
The NBSG86A employs input default circuitry so that under open
input conditions (D
x
, D
x
, VTD
x
, VTD
x,
VTSEL) the outputs of the
device will remain stable.
Features
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MARKING
DIAGRAM*
16
1
QFN16
MN SUFFIX
CASE 485G
•
•
•
•
•
•
•
•
•
Maximum Input Clock Frequency > 8 GHz Typical
Maximum Input Data Rate > 8 Gb/s Typical
165 ps Typical Propagation Delay
40 ps Typical Rise and Fall Times
Selectable Swing PECL Output with Operating Range:
V
CC
= 2.375 V to 3.465 V with V
EE
= 0 V
Selectable Swing NECL Output with NECL Inputs with
Operating Range: V
CC
= 0 V with V
EE
= −2.375 V to −3.465 V
Selectable Output Level (0 V, 200 mV, 400 mV,
600 mV, or 800 mV Peak−to−Peak Output)
50
W
Internal Input Termination Resistors
This is a Pb−Free Device
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information on page 16 of
this data sheet.
©
Semiconductor Components Industries, LLC, 2014
1
January, 2018 − Rev. 20
Publication Order Number:
NBSG86A/D
ÇÇ
1
SG
86A
ALYWG
G
NBSG86A
VTD0 D0
16
OLS
SEL
SEL
VTSEL
15
D0
14
VTD0
13
Exposed Pad
(EP)
12
11
NBSG86A
3
4
10
9
Q
V
CC
V
EE
Q
1
2
5
VTD1
6
D1
7
8
D1 VTD1
Figure 1. QFN16 Pinout
(Top View)
Table 1. Pin Description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
−
Name
OLS
(Note 3)
SEL
SEL
VTSEL
VTD1
D1
D1
VTD1
V
CC
Q
Q
V
EE
VTD0
D0
D0
VTD0
EP
I/O
Input
ECL, CML, LVCMOS,
LVDS, LVTTL Input
ECL, CML, LVCMOS,
LVDS, LVTTL Input
−
−
ECL, CML, LVCMOS,
LVDS, LVTTL Input
ECL, CML, LVCMOS,
LVDS, LVTTL Input
−
−
RSECL Output
RSECL Output
−
−
ECL, CML, LVCMOS,
LVDS, LVTTL Input
ECL, CML, LVCMOS,
LVDS, LVTTL Input
−
−
Description
Input Pin for the Output Level Select (OLS). See Table 2.
Inverted Differential Select Logic Input.
Noninverted Differential Select Logic Input.
Common Internal 50
W
Termination Pin for SEL/SEL. See Table 7. (Note 1)
Internal 50
W
termination pin. See Table 7. (Note 1)
Noninverted Differential Input 1. Internal 75 kW to V
EE
.
Inverted Differential Input 1. Internal 75 kW to V
EE
and 36.5 kW to V
CC
.
Internal 50
W
Termination Pin. See Table 7. (Note 1)
Positive Supply Voltage (Note 2)
Noninverted Differential Output. Typically Terminated with 50
W
Resistor to V
TT
= V
CC
−
2 V.
Inverted Differential Output. Typically Terminated with 50
W
Resistor to V
TT
= V
CC
− 2 V
Negative Supply Voltage (Note 2)
Internal 50
W
Termination Pin. See Table 7. (Note 1)
Inverted Differential Input 0. Internal 75 kW to V
EE
and 36.5 kW to V
CC
.
Noninverted Differential Input 0. Internal 75 kW to V
EE
.
Internal 50
W
Termination Pin. See Table 7. (Note 1)
The Exposed Pad (EP) and the QFN−16 package bottom is thermally connected to the die
for improved heat transfer out of package. The exposed pad must be attached to a heat−
sinking conduit. The pad is electrically connected to the die but may be electrically and
thermally connected to V
EE
on the PC board.
1. In the differential configuration when the input termination pins (VTDx, VTDx, VTSEL) are connected to a common termination voltage,
or left open, and if no signal is applied then the device will be susceptible to self−oscillation.
2. All V
CC
and V
EE
pins must be externally connected to Power Supply to guarantee proper operation.
3. When an output level of 400 mV is desired and V
CC
− V
EE
> 3.0 V, 2 kW resistor should be connected from OLS pin to V
EE
.
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2
NBSG86A
Table 2. OUTPUT LEVEL SELECT OLS
OLS
V
CC
V
CC
− 0.4 V
V
CC
− 0.8 V
V
CC
− 1.2 V
V
EE
(Note 4)
Float
Q/Q VPP
800 mV
200 mV
600 mV
0
400 mV
600 mV
OLS Sensitivity
OLS − 75 mV
OLS
$
150 mV
OLS
$
100 mV
OLS
$
75 mV
OLS
$
100 mV
N/A
4. When an output level of 400 mV is desired and V
CC
− V
EE
> 3.0 V, 2.0 kW resistor should be
connected from OLS to V
EE
.
50
W
VTD0
D0
R
1
D0
VTD0
50
W
50
W
VTD1
D1
R
1
D1
VTD1
50
W
VTSEL
SEL
SEL
R
1
R
2
50
W
50
W
V
CC
V
EE
R
1
Q
Q
R
2
Figure 2. Logic Diagram
50
W
VTD0
VT or
V
BB
V
CC
VTD0
VTD1
50
W
50
W
D0
D0
Q
Q
D1
D1
VTD1
50
W
50
W
50
W
D0
0
0
0
0
Table 3. AND/NAND TRUTH TABLE
(Note 5)
m
D1
0
0
1
1
b
SEL
0
1
0
1
m
*
b
Q
0
0
0
1
m
5. D0, D1, SEL are inverse of D0, D1, SEL unless specified other-
wise.
VTSEL
SEL
b
SEL
Figure 3. Configuration for AND/NAND Function
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NBSG86A
50
W
VTD0
m
VTD0
50
W
50
W
VTD1
V
CC
VT or V
BB
VTD1
50
W
D0
D0
Q
Q
D1
D1
50
W
50
W
Table 4. OR/NOR TRUTH TABLE**
m
D0
0
0
1
1
D1
1
1
1
1
b
SEL
0
1
0
1
m
or
b
Q
0
1
1
1
** D0, D1, SEL are inverse of D0, D1, SEL unless specified
otherwise.
VTSEL
SEL
b
SEL
Figure 4. Configuration for OR/NOR Function
50
W
VTD0
m
VTD0
50
W
50
W
VTD1
D0
D0
Q
Q
D1
D1
Table 5. XOR/XNOR TRUTH TABLE**
m
D0
0
0
1
50
W
1
D1
1
1
0
0
b
SEL
0
1
0
1
m
XOR
b
Q
0
1
1
0
VTD1
50
W
50
W
VTSEL
SEL
** D0, D1, SEL are inverse of D0, D1, SEL unless specified oth-
erwise.
SEL
b
Figure 5. Configuration for XOR/XNOR Function
50
W
VTD0
D0
D0
VTD0
50
W
50
W
VTD1
D1
D1
VTD1
50
W
50
W
50
W
Q
Q
Table 6. 2:1 MUX TRUTH TABLE**
SEL
1
0
Q
D1
D0
** D0, D1, SEL are inverse of D0, D1, SEL unless specified
otherwise.
VTSEL
SEL
SEL
Figure 6. Configuration for 2:1 MUX Function
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NBSG86A
Table 7. Interfacing Options
INTERFACING OPTIONS
CML
LVDS
AC−COUPLED
RSECL, PECL, NECL
LVTTL, LVCMOS
CONNECTIONS
Connect VTD0, VTD1, VTSEL and VTD0, VTD1 to V
CC
Connect VTD0, VTD1, VTD0 and VTD1 together. Leave VTSEL open.
Bias VTD0, VTD1, VTSEL and VTD0, VTD1 Inputs within (VIHCMR) Common Mode Range
Standard ECL Termination Techniques
An external voltage should be applied to the unused complementary differential input.
Nominal voltage 1.5 V for LVTTL and V
CC
/2 for LVCMOS inputs.
Table 8. ATTRIBUTES
Characteristics
Internal Input Pulldown Resistors
Internal Input Pullup Resistor
ESD Protection
(R
1
)
(R
2
)
Human Body Model
Machine Model
Charged Device Model
Pb−Free
Oxygen Index: 28 to 34
Value
75 kW
37.5 kW
> 1 KV
> 50 V
> 4 KV
Level 1
UL 94 V−0 @ 0.125 in
Moisture Sensitivity (Note 6)
Flammability Rating
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
6. For additional information, see Application Note AND8003/D.
Table 9. MAXIMUM RATINGS
Symbol
V
CC
V
EE
V
I
V
INPP
I
IN
I
out
T
A
T
stg
q
JA
q
JC
T
sol
Parameter
Positive Power Supply
Negative Power Supply
Positive Input
Negative Input
Differential Input Voltage |D
n
− D
n
|, |SEL − SEL|
Input Current Through R
T
(50
W
Resistor)
Output Current
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient)
(Note 7)
Thermal Resistance (Junction−to−Case)
Wave Solder
Pb−Free
0 lfpm
500 lfpm
2S2P (Note 7)
< 3 sec @ 260°C
Condition 1
V
EE
= 0 V
V
CC
= 0 V
V
EE
= 0 V
V
CC
= 0 V
V
CC
− V
EE
w
2.8 V
V
CC
− V
EE
< 2.8 V
Static
Surge
Continuous
Surge
V
I
v
V
CC
V
I
w
V
EE
Condition 2
Rating
3.6
−3.6
3.6
−3.6
2.8
|V
CC
− V
EE
|
45
80
25
50
−40 to +85
−65 to +150
41.6
35.2
4.0
265
Unit
V
V
V
V
V
V
mA
mA
mA
mA
°C
°C
°C/W
°C/W
°C/W
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
7. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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