NB7VQ14M
1.8V/2.5V/3.3V 8GHz /
14Gbps Differential 1:4
Clock / Data CML Fanout
Buffer
w/ Selectable Input
Equalizer
Multi−Level Inputs w/ Internal Termination
Description
1
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MARKING
DIAGRAM*
16
The NB7VQ14M is a high performance differential 1:4 CML fanout
buffer with a selectable Equalizer receiver. When placed in series with
a Clock /Data path operating up to 8 GHz or 14 Gb/s, respectively, the
NB7VQ14M inputs will compensate the degraded signal transmitted
across a FR4 PCB backplane or cable interconnect and output four
identical CML copies of the input signal with a 1.8 V, 2.5 V or 3.3 V
power supply. Therefore, the serial data rate is increased by reducing
Inter−Symbol Interference (ISI) caused by losses in copper
interconnect or long cables. The EQualizer ENable pin (EQEN)
allows the IN/IN inputs to either flow through or bypass the Equalizer
section. Control of the Equalizer function is realized by setting EQEN;
When EQEN is set Low, the IN/IN inputs bypass the Equalizer. When
EQEN is set High, the IN/IN inputs flow through the Equalizer. The
default state at start−up is LOW. As such, NB7VQ14M is ideal for
SONET, GigE, Fiber Channel, Backplane and other Clock/Data
distribution applications.
The differential inputs incorporate internal 50
W
termination
resistors that are accessed through the VT pin. This feature allows the
NB7VQ14M to accept various logic level standards, such as LVPECL,
CML or LVDS. The 1:4 fanout design was optimized for low output
skew applications.
The NB7VQ14M is a member of the GigaComm™ family of high
performance clock products.
Features
1
QFN−16
MN SUFFIX
CASE 485G
NB7V
Q14M
ALYWG
G
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
SIMPLIFIED BLOCK DIAGRAM
EQ
•
•
•
•
•
•
•
•
•
•
•
•
•
Input Data Rate > 14 Gb/s, Typical
Input Clock Frequency > 8 GHz, Typical
165 ps Typical Propagation Delay
30 ps Typical Rise and Fall Times
< 15 ps Maximum Output Skew
< 0.8 ps Maximum RMS Clock Jitter
< 10 ps pp of Data Dependent Jitter
Differential CML Outputs, 400 mV Peak−to−Peak, Typical
Selectable Input Equalization
Operating Range: V
CC
= 1.71 V to 3.6 V with GND = 0 V
Internal Input Termination Resistors, 50
W
−40°C
to +85°C Ambient Operating Temperature
These are Pb−Free Devices
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
©
Semiconductor Components Industries, LLC, 2010
December, 2010
−
Rev. 0
1
Publication Order Number:
NB7VQ14M/D
NB7VQ14M
Multi−Level Inputs
LVPECL, LVDS, CML
IN
VT
IN
50
W
CML Outputs
Q0
50
W
0
2:1
MUX
EQ
1
Q0
Q1
Q1
Q2
Q2
Q3
Q3
75 kW
VREFAC
V
CC
GND
EQEN
(Equalizer Enable)
Figure 1. Detailed Block Diagram of NB7VQ14M
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2
NB7VQ14M
GND Q0
16
IN
VT
1
2
NB7VQ14M
VREFAC 3
IN
4
5
6
7
Q3
8
V
CC
15
Q0
14
V
CC
Exposed Pad (EP)
13
12 Q1
11 Q1
10 Q2
9
Q2
Table 1. EQUALIZER ENABLE FUNCTION
EQEN
0
1
Function
IN / IN Inputs By−pass the Equalizer section
Inputs flow through the Equalizer
EQEN Q3
Figure 2. QFN−16 Pinout
(Top View)
Table 2. PIN DESCRIPTION
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
−
Name
IN
VT
VREFAC
IN
EQEN
Q3
Q3
VCC
Q2
Q2
Q1
Q1
VCC
Q0
Q0
GND
EP
LVPECL, CML,
LVDS Input
LVCMOS Input
CML Output
CML Output
−
CML Output
CML Output
CML Output
CML Output
−
CML Output
CML Output
−
−
I/O
LVPECL, CML,
LVDS Input
Non−inverted Differential Input. Note 1.
Internal 100
W
Center−tapped Termination Pin for IN / IN
Output Voltage Reference for Capacitor−Coupled Inputs, only
Inverted Differential Input. Note 1.
Equalizer Enable Input; pin will default LOW when left open (has internal pull−down resistor)
Inverted Differential Output. Typically Terminated with 50
W
Resistor to V
CC
.
Non−inverted Differential Output. Typically Terminated with 50
W
Resistor to V
CC
.
Positive Supply Voltage
Inverted Differential Output. Typically Terminated with 50
W
Resistor to V
CC
.
Non−inverted Differential Output. Typically Terminated with 50
W
Resistor to V
CC
.
Inverted Differential Output. Typically Terminated with 50
W
Resistor to V
CC
.
Non−inverted Differential Output. Typically Terminated with 50
W
Resistor to V
CC
.
Positive Supply Voltage
Inverted Differential Output. Typically Terminated with 50
W
Resistor to V
CC
.
Non−inverted Differential Output. Typically Terminated with 50
W
Resistor to V
CC
.
Negative Supply Voltage
The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected to the die for
improved heat transfer out of package. The exposed pad must be attached to a heat−sinking
conduit. The pad is electrically connected to the die, and must be electrically and thermally con-
nected to GND on the PC board.
Description
1. In the differential configuration when the input termination pin (VT) is connected to a common termination voltage or left open, and if no signal
is applied on IN / IN input, then, the device will be susceptible to self−oscillation.
2. All VCC and GND pins must be externally connected to a power supply for proper operation.
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3
NB7VQ14M
Table 3. ATTRIBUTES
Characteristics
ESD Protection
R
PD
−
EQEN Input Pulldown Resistor
Moisture Sensitivity (Note 3)
Flammability Rating
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
3. For additional information, see Application Note AND8003/D.
16−QFN
Oxygen Index: 28 to 34
Human Body Model
Machine Model
Value
> 2 kV
> 200V
75 kW
Level 1
UL 94 V−0 @ 0.125 in
210
Table 4. MAXIMUM RATINGS
Symbol
V
CC
V
IO
V
INPP
I
IN
I
OUT
I
VFREFAC
T
A
T
stg
θ
JA
θ
JC
T
sol
Parameter
Positive Power Supply
−
Core
Positive Input/Output Voltage
Differential Input Voltage |IN
−
IN|
Input Current Through R
T
(50
W
Resistor)
Output Current Through R
T
(50
W
Resistor)
VREFAC Sink/Source Current
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient) (Note 4)
Thermal Resistance (Junction−to−Case) (Note 4)
Wave Solder
Pb−Free
0 lfpm
500 lfpm
16 QFN
16 QFN
16 QFN
16 QFN
Condition 1
GND = 0 V
GND = 0 V
Condition 2
Rating
4.0
−0.5
to V
CC
+
0.5
1.89
$40
$40
$1.5
−40
to +85
−65
to +150
42
35
4
265
Unit
V
V
V
mA
mA
mA
°C
°C
°C/W
°C/W
°C/W
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
4. JEDEC standard multilayer board
−
2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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NB7VQ14M
Table 5. DC CHARACTERISTICS, MULTI−LEVEL INPUTS
V
CC
= 1.71 V to 3.6 V; GND = 0 V;
Symbol
POWER SUPPLY CURRENT
V
CC
Power Supply Voltage
V
CC
= 3.3 V
V
CC
= 2.5 V
V
CC
= 1.8 V
3.135
2.375
1.71
3.3
2.5
1.8
170
V
CC
– 30
3270
2470
1770
V
CC
– 525
2775
1975
1275
V
CC
– 5
3295
2495
1795
V
CC
– 425
2875
2075
1375
3.6
2.625
1.89
210
V
CC
3300
2500
1800
V
CC
– 325
2975
2175
1475
V
Characteristic
Min
Typ
Max
Unit
T
A
=
−40°C
to 85°C (Note 5)
I
CC
V
OH
Power Supply Current (Inputs and Outputs Open)
Output HIGH Voltage
mA
mV
CML OUTPUTS
(Note 6)
V
CC
= 3.3 V
V
CC
= 2.5 V
V
CC
= 1.8 V
V
CC
= 3.3 V
V
CC
= 2.5 V
V
CC
= 1.8 V
V
OL
Output LOW Voltage
mV
DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED
(see Figures 5 and 7) (Note 7)
V
IH
V
IL
V
th
V
ISE
VREFAC
V
REFAC
Output Reference Voltage @ 100
mA
for capacitor* coupled inputs,
only (Note 9)
V
CC
= 3.3 V
V
CC
= 2.5 V
V
CC
= 1.8 V
Differential Input HIGH Voltage
Differential Input LOW Voltage
Differential Input Voltage (V
IHD
−
V
ILD
)
Input Common Mode Range (Differential Configuration) (Note 10)
(Figure 9)
Input HIGH Current IN / IN, (VT Open)
Input LOW Current IN / IN, (VT Open)
Input HIGH Voltage for Control Pins
Input LOW Voltage for Control Pins
Input HIGH Current
Input LOW Current
Internal Input Termination Resistor
Internal Output Termination Resistor
V
CC
– 650
2650
1850
1150
V
CC
– 500
2800
2000
1300
V
CC
– 350
2950
2150
1450
mV
Single−ended Input HIGH Voltage
Single−ended Input LOW Voltage
Input Threshold Reference Voltage Range (Note 8)
Single−ended Input Voltage Amplitude (V
IH
−
V
IL
)
V
th
+ 100
GND
1050
200
V
CC
V
th
−100
V
CC
−
100
2800
mV
mV
mV
mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY
(see Figures 6 and 8) (Note 9)
V
IHD
V
ILD
V
ID
V
CMR
I
IH
I
IL
V
IH
V
IL
I
IH
I
IL
R
TIN
R
TOUT
1200
0
100
1050
−150
−150
V
CC
x 0.65
GND
−150
−150
45
45
50
50
V
CC
V
IHD
−
100
1200
V
CC
−
50
150
150
V
CC
V
CC
x 0.35
150
150
55
55
mV
mV
mV
mV
mA
mA
V
V
mA
mA
W
W
CONTROL INPUTS
(EQEN)
TERMINATION RESISTORS
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Input and output parameters vary 1:1 with V
CC
.
6. CML outputs loaded with 50
W
to V
CC
for proper operation.
7. V
th
, V
IH
, V
IL,,
and V
ISE
parameters must be complied with simultaneously.
8. V
th
is applied to the complementary input when operating in single−ended mode.
9. V
IHD
, V
ILD,
V
ID
and V
CMR
parameters must be complied with simultaneously.
10. V
CMR
min varies 1:1 with GND, V
CMR
max varies 1:1 with V
CC
. The V
CMR
range is referenced to the crosspoint side of the differential input
signal.
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