$GYDQFHG 3RZHU 026)(7
FEATURES
♦
Avalanche Rugged Technology
♦
Rugged Gate Oxide Technology
♦
Lower Input Capacitance
♦
Improved Gate Charge
♦
Extended Safe Operating Area
♦
Lower Leakage Current: 10µA (Max.) @ V
DS
= 200V
♦
Lower R
DS(ON)
: 0.609Ω (Typ.)
IRLR/U220A
BV
DSS
= 200 V
R
DS(on)
= 0.8Ω
I
D
= 4.6 A
D-PAK
2
1
3
1
I-PAK
2
3
1. Gate 2. Drain 3. Source
Absolute Maximum Ratings
Symbol
V
DSS
I
D
I
DM
V
GS
E
AS
I
AR
E
AR
dv/dt
P
D
Characteristic
Drain-to-Source Voltage
Continuous Drain Current (T
C
=25°C)
Continuous Drain Current (T
C
=100°C)
Drain Current-Pulsed
Gate-to-Source Voltage
Single Pulsed Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Total Power Dissipation (T
A
=25°C) *
Total Power Dissipation (T
C
=25°C)
Linear Derating Factor
T
J
, T
STG
T
L
Operating Junction and
Storage Temperature Range
Maximum Lead Temp. for Soldering
Purposes, 1/8
from case for 5-seconds
(2)
(1)
(1)
(3)
(1)
Value
200
4.6
2.9
16
±20
28
4.6
3.3
5
2.5
33
0.26
- 55 to +150
Units
V
A
A
V
mJ
A
mJ
V/ns
W
W
W/°C
°C
300
Thermal Resistance
Symbol
R
θJC
R
θJA
R
θJA
Characteristic
Junction-to-Case
Junction-to-Ambient *
Junction-to-Ambient
Typ.
--
--
--
Max.
3.7
50
110
°C/W
Units
*
When mounted on the minimum pad size recommended (PCB Mount).
Rev. B
©1999 Fairchild Semiconductor Corporation
1
IRLR/U220A
Electrical Characteristics
(T
C
=25°C unless otherwise specified)
Symbol
BV
DSS
∆BV/∆T
J
V
GS(th)
I
GSS
I
DSS
R
DS(on)
g
fs
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
Q
g
Q
gs
Q
gd
Characteristic
Drain-Source Breakdown Voltage
Breakdown Voltage Temp. Coeff.
Gate Threshold Voltage
Gate-Source Leakage , Forward
Gate-Source Leakage , Reverse
Drain-to-Source Leakage Current
Static Drain-Source
On-State Resistance
Forward Transconductance
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain ( Miller ) Charge
Min. Typ. Max. Units
200
--
1.0
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
0.18
--
--
--
--
--
--
3.3
330
55
25
8
6
24
6
10.3
2.0
4.4
--
--
2.0
100
-100
10
100
0.8
--
430
70
30
25
20
60
20
15
--
--
nC
ns
pF
µA
Ω
Ω
V
V
nA
1&+$11(/
32:(5 026)(7
Test Condition
V
GS
=0V,I
D
=250µA
V/°C I
D
=250µA
V
GS
=20V
V
GS
=-20V
V
DS
=200V
See Fig 7
V
DS
=5V,I
D
=250µA
V
DS
=160V,T
C
=125°C
V
GS
=5V,I
D
=2.3A
V
DS
=40V,I
D
=2.3A
(4)
(4)
V
GS
=0V,V
DS
=25V,f =1MHz
See Fig 5
V
DD
=100V,I
D
=5A,
R
G
=9Ω
See Fig 13
V
DS
=160V,V
GS
=5V,
I
D
=5A
(4) (5)
See Fig 6 & Fig 12
(4) (5)
Source-Drain Diode Ratings and Characteristics
Symbol
I
S
I
SM
V
SD
t
rr
Q
rr
Characteristic
Continuous Source Current
Pulsed-Source Current
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
(1)
(4)
Min. Typ. Max. Units
--
--
--
--
--
--
--
--
140
0.59
4.6
16
1.5
--
--
A
V
ns
µC
Test Condition
Integral reverse pn-diode
in the MOSFET
T
J
=25°C,I
S
=4.6A,V
GS
=0V
T
J
=25°C,I
F
=5A
di
F
/dt=100A/µs
(4)
Notes;
(1) Repetitive Rating: Pulse Width Limited by Maximum Junction Temperature
(2) L=2mH, I
AS
=4.6A, V
DD
=50V, R
G
=27
Ω
, Starting T
J
=25°C
(3) I
SD
≤
5A, di/dt
≤
180A/µs, V
DD
≤
BV
DSS
, Starting T
J
=25°C
(4) Pulse Test: Pulse Width = 250µs, Duty Cycle
≤
2%
(5) Essentially Independent of Operating Temperature
2
1&+$11(/
32:(5 026)(7
Fig 1. Output Characteristics
V
GS
IRLR/U220A
Fig 2. Transfer Characteristics
1
1
0
1
1
0
Top :
7.0 V
6.0 V
I
D
, Drain Current [A]
4.5 V
4.0 V
1
0
0
3.5 V
Bottom : 3.0V
I
D
, Drain Current [A]
5.5 V
5.0 V
1 0
o
C
5
1
0
0
2
o
C
5
- 5
o
C
5
1
-1
0
@ Nt s:
oe
1 2 0
µ
s P l e T s
. 5
u s et
o
2 T =2 C
.
C
5
1
0
0
DS
@Nts:
oe
1 V =0V
.
GS
2 V =4 V
.
DS
0
us et
3 2 0
µ
s P l e T s
. 5
4
6
8
1
0
1
-1
0
1
1
0
1
-1
0
0
2
V , Drain-Source Voltage [V]
V
GS
, Gate-Source Voltage [V]
20
.
Fig 3. On-Resistance vs. Drain Current
I
DR
, Reverse Drain Current [A]
1
1
0
Fig 4. Source-Drain Diode Forward Voltage
R
DS(on)
, [
Ω
]
Drain-Source On-Resistance
15
.
V =5 V
GS
10
.
1
0
0
05
.
V =1 V
0
GS
@ N t : T = 2
o
C
oe
J
5
00
.
0
3
6
9
1
2
1
5
1
8
1 0
o
C
5
2
o
C
5
1
-1
0
04
.
06
.
08
.
10
.
12
.
@Nts:
oe
1 V =0V
.
GS
us et
2 2 0
µ
s P l e T s
. 5
14
.
16
.
18
.
I
D
, Drain Current [A]
V
SD
, Source-Drain Voltage [V]
Fig 5. Capacitance vs. Drain-Source Voltage
50
0
C = C + C (C = so td )
iss gs gd
ds
h r e
C =C +C
oss ds gd
C =C
rss gd
6
Fig 6. Gate Charge vs. Gate-Source Voltage
40
0
C
iss
V =4 V
0
DS
V
GS
, Gate-Source Voltage [V]
Capacitance [pF]
V =10V
0
DS
V =10V
6
DS
4
30
0
20
0
C
oss
@ Nt s:
oe
1 V =0 V
.
GS
2 f= 1M z
.
H
2
10
0
C
rss
@Nts:I =5A
oe
D
0
0
2
G
0
0
1
0
1
1
0
4
6
8
1
0
1
2
V
DS
, Drain-Source Voltage [V]
Q , Total Gate Charge [nC]
3
IRLR/U220A
Fig 7. Breakdown Voltage vs. Temperature
12
.
25
.
1&+$11(/
32:(5 026)(7
Fig 8. On-Resistance vs. Temperature
Drain-Source Breakdown Voltage
R
DS(on)
, (Normalized)
Drain-Source On-Resistance
20
.
BV
DSS
, (Normalized)
11
.
15
.
10
.
10
.
@Nts:
oe
1 V =5V
.
GS
2 I =25A
.
D
.
-0
5
-5
2
0
2
5
5
0
7
5
10
0
o
09
.
@ Nt s:
oe
1 V =0 V
.
GS
2 I = 2 0
µ
A
.
D
5
05
.
08
.
-5
7
-0
5
-5
2
J
0
2
5
5
0
7
5
10
0
o
15
2
10
5
15
7
00
.
-5
7
15
2
10
5
15
7
T , Junction Temperature [ C]
T
J
, Junction Temperature [ C]
Fig 9. Max. Safe Operating Area
O ea in i Ti Ae
pr to n hs r a
i L m t d b R
DS(on)
s i ie y
1
1
0
1 0
µ
s
0
1m
s
1 m
0 s
1
0
0
@ Nt s:
oe
1 T = 2
o
C
.
C
5
1
0
-1
Fig 10. Max. Drain Current vs. Case Temperature
6
I
D
, Drain Current [A]
5
I
D
, Drain Current [A]
4
D
C
3
2
2 T = 1 0
o
C
.
J
5
3 Sn l P le
. ig e us
1
1
0
0
DS
1
1
0
1
2
0
0
2
5
5
0
7
5
10
0
15
2
10
5
V , Drain-Source Voltage [V]
T
c
, Case Temperature [
o
C]
Fig 11. Thermal Response
Thermal Response
D=0.5
10
0
0.2
0.1
0.05
10
- 1
0.02
0.01
single pulse
@ Notes :
1. Z
J C
(t)=3.17
o
C/W Max.
θ
2. Duty Factor, D=t
1
/t
2
3. T
J M
-T
C
=P
D M
*Z
P
DM
t
1
t
2
θ
JC
(t)
Z (t) ,
θ
JC
10
- 5
10
- 4
10
- 3
10
- 2
10
- 1
10
0
10
1
t
1
, Square Wave Pulse Duration
[sec]
4
1&+$11(/
32:(5 026)(7
IRLR/U220A
Fig 12. Gate Charge Test Circuit & Waveform
Current Regulator
50kΩ
12V
200nF
300nF
Same Type
as DUT
V
GS
Q
g
5V
V
DS
V
GS
DUT
3mA
Q
gs
Q
gd
R
1
Current Sampling (I
G
)
Resistor
R
2
Current Sampling (I
D
)
Resistor
Charge
Fig 13. Resistive Switching Test Circuit & Waveforms
R
L
V
out
V
in
R
G
DUT
V
in
5V
t
d(on)
t
on
t
r
t
d(off)
t
off
t
f
10%
V
out
V
DD
( 0.5 rated V
DS
)
90%
Fig 14. Unclamped Inductive Switching Test Circuit & Waveforms
L
L
V
DS
Vary t
p
to obtain
required peak I
D
BV
DSS
1
2
--------------------
E
AS
= ---- L
L
I
AS
2
BV
DSS
-- V
DD
BV
DSS
I
AS
C
V
DD
V
DD
t
p
I
D
R
G
DUT
5V
t
p
I
D
(t)
V
DS
(t)
Time
5
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
