74HC40105; 74HCT40105
4-bit x 16-word FIFO register
Rev. 4 — 29 January 2016
Product data sheet
1. General description
The 74HC40105; 74HCT40105 is a first-in/first-out (FIFO) "elastic" storage register that
can store 16 4-bit words. It can handle input and output data at different shifting rates.
This feature makes it particularly useful as a buffer between asynchronous systems. Each
word position in the register is clocked by a control flip-flop, which stores a marker bit. A
logic 1 signifies that the data at that position is filled and a logic 0 denotes a vacancy in
that position. The control flip-flop detects the state of the preceding flip-flop and
communicates its own status to the succeeding flip-flop. When a control flip-flop is in the
logic 0 state and sees a logic 1 in the preceding flip-flop, it generates a clock pulse. The
clock pulse transfers data from the preceding four data latches into its own four data
latches and resets the preceding flip-flop to logic 0. The first and last control flip-flops have
buffered outputs. All empty locations "bubble" automatically to the input end, and all valid
data ripples through to the output end. As a result, the status of the first control flip-flop
(data-in ready output - DIR) indicates if the FIFO is full. The status of the last flip-flop
(data-out ready output - DOR) indicates whether the FIFO contains data. As the earliest
data is removed from the bottom of the data stack (output end), all data entered later will
automatically ripple toward the output. Inputs include clamp diodes that enable the use of
current limiting resistors to interface inputs to voltages in excess of V
CC
.
2. Features and benefits
Independent asynchronous inputs and outputs
Expandable in either direction
Reset capability
Status indicators on inputs and outputs
3-state outputs
Input levels:
For 74HC40105: CMOS level
For 74HCT40105: TTL level
3-state outputs
Complies with JEDEC standard JESD7A
ESD protection:
HBM JESD22-A114F exceeds 2 000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from
40 C
to +85
C
and from
40 C
to +125
C
Nexperia
74HC40105; 74HCT40105
4-bit x 16-word FIFO register
3. Ordering information
Table 1.
Ordering information
Package
Temperature
range
74HC40105D
74HCT40105D
74HC40105DB
74HCT40105DB
74HC40105PW
40 C
to +125
C
TSSOP16
40 C
to +125
C
SSOP16
40 C
to +125
C
Name
SO16
Description
plastic small outline package; 16 leads;
body width 3.9 mm
plastic shrink small outline package; 16 leads;
body width 5.3 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
Version
SOT109-1
SOT338-1
SOT403-1
Type number
4. Functional diagram
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
74HC_HCT40105
All information provided in this document is subject to legal disclaimers.
.
Product data sheet
Rev. 4 — 29 January 2016
©
2 of 36
Nexperia B.V. 2017. All rights reserved
Nexperia
74HC40105; 74HCT40105
4-bit x 16-word FIFO register
Fig 3.
Functional diagram
LOW on S input of FF1 and FF5 sets Q output to HIGH independent of state on R input.
LOW on R input of FF2, FF3 and FF4 sets Q output to LOW independent of state on S input.
Fig 4.
Logic diagram
74HC_HCT40105
All information provided in this document is subject to legal disclaimers.
.
Product data sheet
Rev. 4 — 29 January 2016
©
3 of 36
Nexperia B.V. 2017. All rights reserved
Nexperia
74HC40105; 74HCT40105
4-bit x 16-word FIFO register
5. Pinning information
5.1 Pinning
Fig 5.
Pin configuration SO16
Fig 6.
Pin configuration (T)SSOP16
5.2 Pin description
Table 2.
Symbol
OE
DIR
SI
D0 to D3
GND
MR
Q0 to Q3
DOR
SO
V
CC
Pin description
Pin
1
2
3
4, 5, 6, 7
8
9
13, 12, 11, 10
14
15
16
Description
output enable input (active LOW)
data-in-ready output
shift-in input (LOW-to-HIGH, edge triggered)
parallel data input
ground (0 V)
asynchronous master-reset input (active HIGH)
data output
data-out-ready output
shift-out input (HIGH-to-LOW, edge triggered)
supply voltage
74HC_HCT40105
All information provided in this document is subject to legal disclaimers.
.
Product data sheet
Rev. 4 — 29 January 2016
©
4 of 36
Nexperia B.V. 2017. All rights reserved
Nexperia
74HC40105; 74HCT40105
4-bit x 16-word FIFO register
6. Functional description
6.1 Inputs and outputs
6.1.1 Data inputs (D0 to D3)
As there is no weighting of the inputs, any input can be assigned as the MSB. The size of
the FIFO memory can be reduced from the 4 x 16 configuration. For example, it can be
reduced to 3 x 16, down to 1 x 16, by tying unused data input pins to V
CC
or GND.
6.1.2 Data outputs (Q0 to Q3)
As there is no weighting of the outputs, any output can be assigned as the MSB. The size
of the FIFO memory can be reduced from the 4 x 16 configuration as described for data
inputs. In a reduced format, the unused data outputs pins must be left open circuit.
6.1.3 Master-reset (MR)
When MR is HIGH, the control functions within the FIFO are cleared, and date content is
declared invalid. The data-in ready (DIR) flag is set HIGH and the data-out-ready (DOR)
flag is set LOW. The output stage remains in the state of the last word that was shifted out,
or in the random state existing at power-up.
6.1.4 Status flag outputs (DIR, DOR)
Two status flags, data-in-ready (DIR) and data-out-ready (DOR), indicate the status of the
FIFO:
1. DIR = HIGH indicates that the input stage is empty and ready to accept valid data;
2. DIR = LOW indicates that the FIFO is full or that a previous shift-in operation is not
complete (busy);
3. DOR = HIGH assures valid data is present at the outputs Q0 to Q3 (does not indicate
that new data is awaiting transfer into the output stage);
4. DOR = LOW indicates that the output stage is busy or there is no valid data.
6.1.5 Shift-in control (SI)
Data is loaded into the input stage on a LOW-to-HIGH transition of SI. It also triggers an
automatic data transfer process (ripple through). If SI is held HIGH during reset, data is
loaded at the falling edge of the MR signal.
6.1.6 Shift-out control (SO)
A HIGH-to-LOW transition of SO causes the DOR flags to go LOW. A HIGH-to-LOW
transition of SO causes upstream data to move into the output stage, and empty locations
to move towards the input stage (bubble-up).
6.1.7 Output enable (OE)
The outputs Q0 to Q3 are enabled when OE = LOW. When OE = HIGH the outputs are in
the high impedance OFF-state.
74HC_HCT40105
All information provided in this document is subject to legal disclaimers.
.
Product data sheet
Rev. 4 — 29 January 2016
©
5 of 36
Nexperia B.V. 2017. All rights reserved
PCB设计
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