CY7C1365C
9-Mbit (256 K × 32)
Flow-Through Sync SRAM
9-Mbit (256 K × 32) Flow-Through Sync SRAM
Features
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Functional Description
The CY7C1365C is a 256 K × 32 synchronous cache RAM
designed to interface with high-speed microprocessors with
minimum glue logic. Maximum access delay from clock rise is
6.5 ns (133-MHz version). A 2-bit on-chip counter captures the
first address in a burst and increments the address automatically
for the rest of the burst access. All synchronous inputs are gated
by registers controlled by a positive-edge-triggered Clock Input
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining Chip Enable (CE
1
), depth-expansion
Chip Enables (CE
2
and CE
3
), Burst Control inputs (ADSC,
ADSP, and ADV), Write Enables (BW[A:D], and BWE), and
Global Write (GW). Asynchronous inputs include the Output
Enable (OE) and the ZZ pin.
The CY7C1365C allows either interleaved or linear burst
sequences, selected by the MODE input pin. A HIGH selects an
interleaved burst sequence, while a LOW selects a linear burst
sequence. Burst accesses can be initiated with the Processor
Address Strobe (ADSP) or the cache Controller Address Strobe
(ADSC) inputs. Address advancement is controlled by the
Address Advancement (ADV) input.
Addresses and Chip Enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or Address
Strobe Controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
Advance pin (ADV).
The CY7C1365C operates from a +3.3 V core power supply
while all outputs may operate with either a +2.5 or +3.3 V supply.
All
inputs
and
outputs
are
JEDEC-standard
JESD8-5-compatible.
256 K × 32 common I/O
3.3 V core power supply (V
DD
)
2.5 V/3.3 V I/O power supply (V
DDQ
)
Fast clock-to-output times
❐
6.5 ns (133-MHz version)
Provide high-performance 2-1-1-1 access rate
User-selectable burst counter supporting Intel
Pentium
interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self-timed write
Asynchronous output enable
Supports 3.3 V I/O level
Available in 165-Ball FBGA package
“ZZ” Sleep Mode option
IEEE 1149.1 JTAG-compatible boundary scan
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Selection Guide
Description
Maximum Access Time
Maximum Operating Current
Maximum Standby Current
133 MHz
6.5
250
40
Unit
ns
mA
mA
Cypress Semiconductor Corporation
Document Number: 001-74584 Rev. *C
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised October 25, 2012
CY7C1365C
Logic Block Diagram – CY7C1365C
A0, A1, A
ADDRESS
REGISTER
A
[1:0]
MODE
ADV
CLK
BURST Q1
COUNTER
AND LOGIC
Q0
CLR
ADSC
ADSP
DQ
D
BW
D
BYTE
WRITE REGISTER
DQ
C
BYTE
WRITE REGISTER
DQ
B
BYTE
WRITE REGISTER
DQ
A
BW
A
BWE
GW
CE1
CE2
CE3
OE
DQ
A
BYTE
WRITE REGISTER
BYTE
WRITE REGISTER
DQ
D
BYTE
WRITE REGISTER
DQ
C
BYTE
WRITE REGISTER
DQ
B
BW
B
BYTE
WRITE REGISTER
BW
C
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
BUFFERS
DQs
ENABLE
REGISTER
INPUT
REGISTERS
ZZ
SLEEP
CONTROL
Document Number: 001-74584 Rev. *C
Page 2 of 30
CY7C1365C
Contents
Pin Configurations ........................................................... 4
Pin Descriptions ............................................................... 5
Functional Overview ........................................................ 7
Single Read Accesses ................................................ 7
Single Write Accesses Initiated by ADSP ................... 7
Single Write Accesses Initiated by ADSC ................... 7
Burst Sequences ......................................................... 7
Sleep Mode ................................................................. 7
Interleaved Burst Address Table
(MODE = Floating or VDD) ................................................. 7
Linear Burst Address Table (MODE = GND) ............... 7
ZZ Mode Electrical Characteristics .............................. 8
Truth Table ........................................................................ 9
Truth Table for Read/Write ............................................ 10
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 11
Disabling the JTAG Feature ...................................... 11
Test Access Port (TAP) ............................................. 11
PERFORMING A TAP RESET .................................. 11
TAP REGISTERS ...................................................... 11
TAP Instruction Set ................................................... 12
TAP Controller State Diagram ....................................... 13
TAP Controller Block Diagram ...................................... 14
TAP Timing ...................................................................... 14
TAP AC Switching Characteristics ............................... 15
3.3 V TAP AC Test Conditions ....................................... 15
3.3 V TAP AC Output Load Equivalent ......................... 15
2.5 V TAP AC Test Conditions ....................................... 15
2.5 V TAP AC Output Load Equivalent ......................... 15
TAP DC Electrical Characteristics and
Operating Conditions ..................................................... 16
Identification Register Definitions ................................ 16
Scan Register Sizes ....................................................... 16
Instruction Codes ........................................................... 17
Boundary Scan Order .................................................... 18
Maximum Ratings ........................................................... 19
Operating Range ............................................................. 19
Electrical Characteristics ............................................... 19
Capacitance .................................................................... 20
Thermal Resistance ........................................................ 20
AC Test Loads and Waveforms ..................................... 20
Switching Characteristics .............................................. 21
Timing Diagrams ............................................................ 22
Ordering Information ...................................................... 26
Ordering Code Definitions ......................................... 26
Package Diagram ............................................................ 27
Acronyms ........................................................................ 28
Document Conventions ................................................. 28
Units of Measure ....................................................... 28
Document History Page ................................................. 29
Sales, Solutions, and Legal Information ...................... 30
Worldwide Sales and Design Support ....................... 30
Products .................................................................... 30
PSoC Solutions ......................................................... 30
Document Number: 001-74584 Rev. *C
Page 3 of 30
CY7C1365C
Pin Configurations
Figure 1. 165-ball FBGA pinout
CY7C1365C (256 K × 32)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
NC/288M
NC/144M
NC
DQ
C
DQ
C
DQ
C
DQ
C
NC
DQ
D
DQ
D
DQ
D
DQ
D
NC
NC
MODE
2
A
A
NC
DQ
C
DQ
C
DQ
C
DQ
C
V
SS
DQ
D
DQ
D
DQ
D
DQ
D
NC
NC/72M
NC/36M
3
CE
1
CE2
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
4
BW
C
BW
D
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
5
BW
B
BW
A
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDI
TMS
6
CE
3
CLK
7
BWE
GW
V
SS
8
ADSC
OE
9
ADV
ADSP
V
DDQ
10
A
A
NC/1G
DQ
B
DQ
B
DQ
B
DQ
B
NC
DQ
A
DQ
A
DQ
A
DQ
A
NC
A
A
11
NC
NC/576M
NC
DQ
B
DQ
B
DQ
B
DQ
B
ZZ
DQ
A
DQ
A
DQ
A
DQ
A
NC
A
A
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC/18M
A1
A0
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDO
TCK
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
A
A
Document Number: 001-74584 Rev. *C
Page 4 of 30
CY7C1365C
Pin Descriptions
Name
A
0
, A
1
, A
I/O
Description
Input-
Address Inputs used to select one of the 256K address locations.
Sampled at the rising edge of the
Synchronous CLK if ADSP or ADSC is active LOW, and CE
1
, CE
2
, and CE
3
are sampled active. A
[1:0]
feed the 2-bit
counter.
BW
A
, BW
B
,
Input-
Byte Write Select Inputs, active LOW.
Qualified with BWE to conduct Byte Writes to the SRAM.
Synchronous Sampled on the rising edge of CLK.
BW
C
, BW
D
GW
BWE
CLK
CE
1
Input-
Global Write Enable Input, active LOW.
When asserted LOW on the rising edge of CLK, a global write
Synchronous is conducted (ALL bytes are written, regardless of the values on BW
[A:D]
and BWE).
Input-
Byte Write Enable Input, active LOW.
Sampled on the rising edge of CLK. This signal must be asserted
Synchronous LOW to conduct a Byte Write.
Input-Clock
Clock Input.
Used to capture all synchronous inputs to the device. Also used to increment the burst
counter when ADV is asserted LOW, during a burst operation.
Input-
Chip Enable 1 Input, active LOW.
Sampled on the rising edge of CLK. Used in conjunction with CE
2
Synchronous and CE
3
to select/deselect the device. ADSP is ignored if CE
1
is HIGH. CE
1
is sampled only when a new
external address is loaded.
Input-
Chip Enable 2 Input, active HIGH.
Sampled on the rising edge of CLK. Used in conjunction with CE
1
Synchronous and CE
3
to select/deselect the device. CE
2
is sampled only when a new external address is loaded.
Input-
Chip Enable 3 Input, active LOW.
Sampled on the rising edge of CLK. Used in conjunction with CE
1
Synchronous and CE
2
to select/deselect the device. CE
3
is assumed active throughout this document for BGA. CE
3
is sampled only when a new external address is loaded.
Input-
Output Enable, asynchronous input, active LOW.
Controls the direction of the I/O pins. When LOW,
Asynchronous the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data
pins. OE is masked during the first clock of a Read cycle when emerging from a deselected state.
Input-
Advance Input signal, sampled on the rising edge of CLK.
When asserted, it automatically increments
Synchronous the address in a burst cycle.
Input-
Address Strobe from Processor, sampled on the rising edge of CLK, active LOW.
When asserted
Synchronous LOW, addresses presented to the device are captured in the address registers. A
[1:0]
are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is
ignored when CE
1
is deasserted HIGH.
Input-
Address Strobe from Controller, sampled on the rising edge of CLK, active LOW.
When asserted
Synchronous LOW, addresses presented to the device are captured in the address registers. A
[1:0]
are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
Input-
ZZ “sleep” Input, active HIGH.
When asserted HIGH places the device in a non-time-critical “sleep”
Asynchronous condition with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ
pin has an internal pull-down.
I/O-
Bidirectional Data I/O lines.
As inputs, they feed into an on-chip data register that is triggered by the
Synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the
addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled
by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs are placed in a tri-state
condition.
Power Supply
Power supply inputs to the core of the device.
Ground
I/O Power
Supply
Ground for the core of the device.
Power supply for the I/O circuitry.
CE
2
CE
3
OE
ADV
ADSP
ADSC
ZZ
DQs
V
DD
V
SS
V
DDQ
V
SSQ
TDO
I/O Ground
Ground for the I/O circuitry.
JTAG serial
Serial data-out to the JTAG circuit.
Delivers data on the negative edge of TCK. If the JTAG feature is
output
not being used, this pin should be left unconnected.
synchronous
Document Number: 001-74584 Rev. *C
Page 5 of 30
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