CYRF6986
WirelessUSB™ LPstar 2.4 GHz
Radio SoC
WirelessUSB™ LPstar 2.4 GHz Radio SoC
Features
■
■
■
■
Simple Development
■
■
■
■
■
■
2.4 GHz direct sequence spread spectrum (DSSS) radio trans-
ceiver
Operates in the unlicensed worldwide Industrial, Scientific, and
Medical (ISM) band (2.400 GHz to 2.483 GHz)
On Air compatible with second generation radio
WirelessUSB™ LP and PRoC LP
Pin-to-pin compatible with WirelessUSB LP except the Pin30
and Pin37
Auto transaction sequencer (ATS): Enables MCU to sleep
longer
Framing, length, CRC16, and auto ACK
Separate 16-byte transmit and receive FIFOs
Receive signal strength indication (RSSI)
Serial peripheral interface (SPI) control while in sleep mode
4 MHz SPI microcontroller interface
Low Power
■
■
■
■
■
BOM Savings
■
■
■
Operating current: 21 mA (transmit at –5 dBm)
Sleep current less than 1
A
Operating voltage: 2.7 V to 3.6 V
Fast startup and fast channel changes
Supports coin-cell operated applications
Low external component count
Battery voltage monitoring circuitry
Small footprint 40-pin QFN (6 mm × 6 mm)
Applications
■
■
■
■
■
■
Wireless keyboards and mice
Presentation tools
Wireless gamepads
Remote controls
Toys
Fitness
Reliable and Robust
■
■
Receive Sensitivity typical –90 dBm
AutoRate™ – dynamic data rate reception
❐
Enables data reception for any of the supported bit rates
automatically.
❐
DSSS (250 Kbps), GFSK (1 Mbps)
Operating Temperature: 0 °C to 70 °C
Closed-loop frequency synthesis for minimal frequency drift
■
■
Applications Support
See
www.cypress.com
for development tools, reference
designs, and application notes.
Logic Block Diagram
IRQ
SS
SCK
MISO
MOSI
Data
Interface
and
Sequencer
SPI
GFSK
Modulator
DSSS
Baseband
& Framer
RF
P
RF
N
RF
BIAS
Frequency
Synthesizer
RSSI
Power Management
RST
V
BAT
V
DD
V
CC
GFSK
Demodulator
GND
Cypress Semiconductor Corporation
Document Number: 001-66073 Rev. *F
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised May 19, 2017
Not recommended for new designs
CYRF6986
Contents
Functional Description ..................................................... 3
Pinouts .............................................................................. 3
Pin Definitions .................................................................. 3
Functional Overview ........................................................ 4
Data Transmission Modes ........................................... 4
Link Layer Modes ........................................................ 4
Packet Buffers ............................................................. 5
Auto Transaction Sequencer (ATS) ............................ 5
Functional Block Overview .............................................. 5
2.4 GHz Radio ............................................................. 5
Frequency Synthesizer ................................................ 6
Baseband and Framer ................................................. 6
Packet Buffers and
Radio Configuration Registers ............................................ 6
SPI Interface ................................................................ 6
Interrupts ..................................................................... 8
Clocks .......................................................................... 8
Power Management .................................................... 8
Low Noise Amplifier and
Received Signal Strength Indication ................................... 8
Application Example ........................................................ 9
Registers ......................................................................... 11
Absolute Maximum Ratings .......................................... 12
Operating Conditions ..................................................... 12
DC Characteristics ......................................................... 12
AC Characteristics ......................................................... 13
SPI Interface .............................................................. 13
RF Characteristics .......................................................... 14
Typical Operating Characteristics ................................ 16
AC Test Loads and Waveforms for Digital Pins .......... 18
Ordering Information ...................................................... 19
Ordering Code Definitions ......................................... 19
Package Diagram ............................................................ 20
Acronyms ........................................................................ 21
Document Conventions ................................................. 21
Units of Measure ....................................................... 21
Document History Page ................................................. 22
Sales, Solutions, and Legal Information ...................... 23
Worldwide Sales and Design Support ....................... 23
Products .................................................................... 23
PSoC® Solutions ...................................................... 23
Cypress Developer Community ................................. 23
Technical Support ..................................................... 23
Document Number: 001-66073 Rev. *F
Page 2 of 23
Not recommended for new designs
CYRF6986
Functional Description
The CYRF6986 WirelessUSB LPstar radio is a second generation member of the Cypress WirelessUSB Radio System-On-Chip (SoC)
family. The CYRF6986 IC adds a range of enhanced features, including reduced supply current in all operating modes, reduced crystal
start up, synthesizer settling, and link turnaround times.
Pinouts
Figure 1. 40-pin QFN pinout
V
BAT0
38
GND 37
RST 34
XTAL
NC
V
CC
NC
NC
V
BAT1
V
CC
V
BAT2
NC
1
2
3
4
5
6
7
8
9
* E-PAD Bottom Side
30 NC
29 XOUT / GPIO
28 MISO / GPIO
CYRF6986
WirelessUSB LPstar
40-Pin QFN
27 MOSI / SDAT
26 IRQ / GPIO
25 SCK
24 SS
23 NC
22 NC
21 NC
RF
BIAS
10
11 RF
P
12 GND
13 RF
N
14 NC
15 NC
16 V
CC
17 NC
18 NC
19 RESV
20 NC
Pin Definitions
Pin Number
1
2, 4, 5, 9, 14,
15, 17, 18, 20,
21, 22, 23, 31,
32, 36, 39
3, 7, 16, 40
6, 8, 38
10
11
12
13
19
24
25
26
27
Name
XTAL
NC
Type
I
NC
Default
I
12 MHz crystal.
Connect to GND.
Description
V
CC
V
BAT(0-2)
RF
BIAS
RF
P
GND
RF
N
RESV
SS
SCK
IRQ
MOSI
Pwr
Pwr
O
I/O
GND
IO
I
I
I
I/O
I/O
I
I
O
I
I
O
I
V
CC
= 2.7 V to 3.6 V.
V
BAT
= 2.7 V to 3.6 V. Main supply.
RF IO 1.8 V reference voltage.
Differential RF signal to and from antenna.
Ground.
Differential RF signal to and from antenna.
Must be connected to GND.
SPI enable, active LOW assertion. Enables and frames transfers.
SPI clock.
Interrupt output (configurable active HIGH or LOW), or GPIO.
SPI data input pin (Master Out Slave In), or SDAT.
Document Number: 001-66073 Rev. *F
Page 3 of 23
Not recommended for new designs
V
CC
40
V
DD
35
NC 36
NC 31
NC 39
NC 32
V
IO
33
CYRF6986
Pin Definitions
(continued)
Pin Number
28
29
30
33
34
Name
MISO
XOUT
NC
V
IO
RST
Type
I/O
I/O
NC
Pwr
I
I
Default
Z
O
Description
SPI data output pin (Master In Slave Out), or GPIO (in SPI 3-pin mode).
Tri-states when SPI 3PIN = 0 and SS is deasserted.
Buffered 0.75, 1.5, 3, 6, or 12 MHz clock or GPIO.
Tri-states in sleep mode (configure as GPIO drive LOW).
Must be floating.
I/O interface voltage, 2.7–3.6 V.
Device reset. Internal 10 k pull down resistor. Active HIGH, connect through
a 0.47
F
capacitor to V
BAT.
Must have RST = 1 event the first time power is
applied to the radio. Otherwise the state of the radio control registers is
unknown.
Decoupling pin for 1.8 V logic regulator, connect through a 0.47
F
capacitor
to GND.
Must be connected to ground.
Must be soldered to ground.
32-chip pseudo noise (PN) codes are supported. The two data
transmission modes apply to the data after the SOP. In particular
the length, data, and CRC16 are all sent in the same mode. In
general, DSSS reduce packet error rate in any given
environment.
35
37
E-PAD
V
DD
GND
GND
Pwr
GND
GND
Functional Overview
The CYRF6986 IC provides a complete WirelessUSB SPI to
antenna wireless MODEMs. The SoC is designed to implement
wireless device links operating in the worldwide 2.4 GHz ISM
frequency band. It is intended for systems compliant with
worldwide regulations covered by ETSI EN 301 489-1 V1.41,
ETSI EN 300 328-1 V1.3.1 (Europe), FCC CFR 47 Part 15 (USA
and Industry Canada), and TELEC ARIB_T66_March, 2003
(Japan).
The SoC contains a 2.4 GHz, 1 Mbps GFSK radio transceiver,
packet data buffering, packet framer, DSSS baseband controller,
Received Signal Strength Indication (RSSI), and SPI interface
for data transfer and device configuration.
The radio supports 98 discrete 1 MHz channels (regulations may
limit the use of some of these channels in certain jurisdictions).
The baseband performs DSSS spreading/despreading, Start of
Packet (SOP), End of Packet (EOP) detection, and CRC16
generation and checking. The baseband may also be configured
to automatically transmit Acknowledge (ACK) handshake
packets whenever a valid packet is received.
When in receive mode, with packet framing enabled, the device
is always ready to receive data transmitted at any of the
supported bit rates. This enables the implementation of
mixed-rate systems in which different devices use different data
rates. This also enables the implementation of dynamic data rate
systems that use high data rates at shorter distances or in a
low-moderate interference environment or both. It changes to
lower data rates at longer distances or in high interference
environments or both.
Link Layer Modes
The CYRF6986 IC device supports the following data packet
framing features:
SOP
Packets begin with a two-symbol SoP marker. If framing is
disabled then an SOP event is inferred whenever two successive
correlations are detected. The SOP_CODE_ADR code used for
the SOP is different from that used for the “body” of the packet,
and if desired may be a different length. SOP must be configured
to be the same length on both sides of the link.
Length
Length field is the first eight bits after the SOP symbol, and is
transmitted at the payload data rate. An EoP condition is inferred
after reception of the number of bytes defined in the length field,
plus two bytes for the CRC16.
CRC16
The device may be configured to append a 16 bit CRC16 to each
packet. The CRC16 uses the USB CRC polynomial with the
added programmability of the seed. If enabled, the receiver
verifies the calculated CRC16 for the payload data against the
received value in the CRC16 field. The seed value for the CRC16
calculation is configurable, and the CRC16 transmitted may be
calculated using either the loaded seed value or a zero seed; the
received data CRC16 is checked against both the configured
and zero CRC16 seeds.
CRC16 detects the following errors:
■
■
Data Transmission Modes
The SoC supports two different data transmission modes:
■
■
In GFSK mode, data is transmitted at 1 Mbps, without any
DSSS.
In DSSS mode eight bits (8DR, 32-chip) are encoded in each
derived code symbol transmitted, resulting in effective 250 kbps
data rate.
Any one bit in error.
Any two bits in error (irrespective of how far apart, which
column, and so on).
Document Number: 001-66073 Rev. *F
Page 4 of 23
Not recommended for new designs
CYRF6986
■
■
Any odd number of bits in error (irrespective of the location).
An error burst as wide as the checksum itself.
Figure 2
shows an example packet with SOP, CRC16, and
lengths fields enabled, and
Figure 3
shows a standard ACK
packet.
Figure 2. Example Packet Format
Preamble N*16us
2nd Framing Symbol*
1st Framing Symbol*
Packet length 1 Byte Period
*Note: 32 us
Figure 3. Example ACK Packet Format
Pream ble N *16us
2nd Fram ing Sym bol*
Pream ble
SOP1
1st Fram ing Sym bol*
SO P2
CRC 16
C R C Field From Received Packet.
2 Byte Periods
*Note: 32 us
Packet Buffers
All data transmission and reception use the 16 byte packet
buffers - one for transmission and one for reception.
The transmit buffer allows loading a complete packet of up to 16
bytes of payload data in one burst SPI transaction. This is then
transmitted with no further MCU intervention. Similarly, the
receive buffer allows receiving an entire packet of payload data
up to 16 bytes with no firmware intervention required until the
packet reception is complete.
The CYRF6986 IC supports packets up to 255 bytes. However,
the actual maximum packet length depends on the accuracy of
the clock on each end of the link and the data mode. Interrupts
are provided to allow an MCU to use the transmit and receive
buffers as FIFOs. When transmitting a packet longer than 16
bytes, the MCU can load 16 bytes initially, and add further bytes
to the transmit buffer as transmission of data creates space in
the buffer. Similarly, when receiving packets longer than 16
bytes, the MCU must fetch received data from the FIFO
periodically during packet reception to prevent it from
overflowing.
Similarly, when receiving in transaction mode, the device
automatically:
■
■
■
Waits in receive mode for a valid packet to be received
Transitions to transmit mode, transmits an ACK packet
Transitions to the transaction end state (receive mode to await
the next packet, and so on.)
The contents of the packet buffers are not affected by the
transmission or reception of ACK packets.
In each case, the entire packet transaction takes place without
any need for MCU firmware action (as long as packets of 16
bytes or less are used). To transmit data, the MCU must load the
data packet to be transmitted, set the length, and set the TX GO
bit. Similarly, when receiving packets in transaction mode,
firmware must retrieve the fully received packet in response to
an interrupt request indicating reception of a packet.
Data Rates
The CYRF6986 IC supports the following data rates by
combining the PN code lengths and data transmission modes
described in the previous sections:
■
■
Auto Transaction Sequencer (ATS)
The CYRF6986 IC provides automated support for transmission
and reception of acknowledged data packets.
When transmitting in transaction mode, the device automatically:
■
■
■
■
■
1000 kbps (GFSK)
250 kbps (32 chip 8DR)
Functional Block Overview
2.4 GHz Radio
The radio transceiver is a dual conversion low IF architecture
optimized for power, range, and robustness. The radio employs
channel-matched filters to achieve high performance in the
presence of interference. An integrated Power Amplifier (PA)
provides up to 0 dBm transmit power, with an output power
Starts the crystal and synthesizer
Enters transmit mode
Transmits the packet in the transmit buffer
Transitions to receive mode and waits for an ACK packet
Transitions to the transaction end state when an ACK packet
is received or a timeout period expires
Document Number: 001-66073 Rev. *F
Page 5 of 23
Not recommended for new designs
Preamble
SOP1
SOP2
Length
<== P a y l o a d ==>
CRC 16
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
