Data Sheet No. PD60208 Rev. E
IR2175(S) & (PbF)
LINEAR CURRENT SENSING IC
Features
•
•
•
•
•
•
•
•
Floating channel up to +600V
Monolithic integration
Linear current feedback through shunt resistor
Direct digital PWM output for easy interface
Low I
QBS
allows the boot strap power supply
Independent fast overcurrent trip signal
High common mode noise immunity
Input overvoltage protection for IGBT short circuit
condition
•
Open Drain outputs
•
Also available LEAD-FREE
Product Summary
V
OFFSET
I
QBS
Vin
Gain temp.drift
fo
Overcurrent trip
signal delay
Overcurrent trip level
600Vmax
2mA
+/-260mVmax
20ppm/
o
C (typ.)
130kHz (typ.)
2µsec (typ)
+/-260mV (typ.)
Description
The IR2175 is a monolithic current sensing IC designed
for motor drive applications. It senses the motor phase
current through an external shunt resistor, converts from
analog to digital signal, and transfers the signal to the
low side. IR’s proprietary high voltage isolation tech-
nology is implemented to enable the high bandwidth
signal processing. The output format is discrete PWM
to eliminate need for the A/D input interface for the
IR2175. The dedicated overcurrent trip (OC) signal fa-
cilitates IGBT short circuit protection. The open-drain
outputs make easy for any interface from 3.3V to 15V. S
Packages
8 Lead PDIP
IR2175
8 Lead SOIC
IR2175S
Block Diagram
Up to 600V
15V
PWM Output
GND
Overcurrent
VCC
PO
V+
VS
IR2175
COM
OC
VB
To Motor Phase
(Refer to Lead Assignments for cor-
rect pin configuration). This/These
diagram(s) show electrical connec-
tions only. Please refer to our Appli-
cation Notes and DesignTips for
proper circuit board layout.
IR2175
(S) & (PbF)
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage
parameters are absolute voltages referenced to COM, all currents are defined positive into any lead. The thermal
resistance and power dissipation ratings are measured under board mounted and still air conditions.
Symbol
V
S
V
BS
V
CC
V
IN
V
PO
V
OC
dV/dt
P
D
Rth
JA
T
J
T
S
T
L
Definition
High side offset voltage
High side floating supply voltage
Low side and logic fixed supply voltage
Maximum input voltage between V
IN+ and
V
S
Digital PWM output voltage
Overcurrent output voltage
Allowable offset voltage slew rate
Package power dissipation @ T
A
≤
+25°C
Thermal resistance, junction to ambient
Junction temperature
Storage temperature
Lead temperature (soldering, 10 seconds)
8 lead SOIC
8 lead PDIP
8 lead SOIC
8 lead PDIP
Min.
-0.3
-0.3
-0.3
-5
COM -0.3
COM -0.3
—
—
—
—
—
—
-55
—
Max.
600
25
25
5
VCC +0.3
VCC +0.3
50
.625
1.0
200
125
150
150
300
Units
V
V/ns
W
°C/W
°C
Note 1: Capacitors are required between V
B
and Vs when bootstrap power is used. The external power supply,
when used, is required between V
B
and Vs pins.
Recommended Operating Conditions
The output logic timing diagram is shown in figure 1. For proper operation the device should be used within the recommended
conditions.
Symbol
V
B
V
S
V
PO
V
OC
V
CC
V
IN
T
A
Definition
High side floating supply voltage
High side floating supply offset voltage
Digital PWM output voltage
Overcurrent output voltage
Low side and logic fixed supply voltage
Input voltage between V
IN+
and V
S
Ambient temperature
Min.
V
S
+13.0
0.3
COM
COM
9.5
-260
-40
Max.
V
S
+20
600
VCC
VCC
20
+260
125
Units
V
mV
°C
2
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IR2175
(S) & (PbF)
DC Electrical Characteristics
V
CC
= V
BS
= 15V, and T
A
= 25
o
unless otherwise specified.
Symbol
V
IN
V
OC+
V
OC-
V
OS
∆
V
OS
/
∆
T
A
G
∆
G
/
∆
T
A
I
LK
I
QBS
I
QCC
LIN
∆
V
LIN
/
∆
T
A
I
OPO
I
OCC
V
IN+ _
V
S
Definition
Nominal input voltage range before saturation
Overcurrent trip positive input voltage
Overcurrent trip negative input voltage
Input offset voltage
Input offset voltage temperature drift
Gain (duty cycle % per V
IN
)
Gain temperature drift
Offset supply leakage current
Quiescent V
BS
supply current
Quiescent V
CC
supply current
Linearity (duty cycle deviation from ideal linearity
curve)
Linearity temperature drift
Digital PWM output sink current
OC output sink current
Min. Typ. Max. Units Test Conditions
-260
—
—
-10
—
155
—
—
—
—
—
—
20
2
10
1
—
260
—
—
10
—
165
—
50
—
0.5
1
—
—
—
—
—
mA
µV/
C
o
260
-260
0
25
160
20
—
2
—
0.5
.005
—
—
—
—
mV
V
IN
= 0V (Note 1)
%/V
ppm/ C
µA
mA
%
%/
o
C
V
O
= 1V
V
O
= 0.1V
V
O
= 1V
V
O
= 0.1V
V
B
= V
S
= 600V
V
S
= 0V
o
max gain error=5%
(Note 2)
Note 1:
±10mV
offset represents
±1.5%
duty cycle fluctuation
Note 2: Gain = (full range of duty cycle in %) / (full input voltage range).
AC Electrical Characteristics
V
CC
= V
BS
= 15V, and T
A
= 25
o
unless otherwise specified.
Symbol
Definition
Propagation delay characteristics
fo
∆
f
/
∆
T
A
Dmin
Dmax
BW
PHS
tdoc
twoc
Carrier frequency output
Temperature drift of carrier frequency
Minimum duty
Maximum duty
fo bandwidth
Phase shift at 1kHz
Propagation delay time of OC
Low true pulse width of OC
Min. Typ. Max. Units Test Conditions
100
—
—
—
—
—
1
—
130
500
9
91
15
-10
2
1.5
180
—
—
—
—
—
—
—
kHz
ppm/ C
%
%
kHz
o
o
figure 1
V
IN
= 0 & 5V
VIN+=-260mV,
VIN+=+260mV
V
IN+ = 100mVpk -pk
sine wave, gain=-3dB
V
IN
+ =100mVpk-pk
sine wave
µsec
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3
IR2175
(S) & (PbF)
Timing Waveforms
PO
Duty=9%
Vin+= -260mV
Vs = 0V
Duty=91%
PO
Vin+= +260mV
Vs = 0V
Carrier Frequency =
130kHz
Figure 1 Output waveform
Application Hint:
Temperature drift of the output carrier frequency can be cancelled by measuring both a PWM period and the on-time
of PWM (Duty) at the same time. Since both periods vary in the same direction, computing the ratio between these
values at each PWM period gives consistent measurement of the current feedback over the temperature drift.
4
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IR2175
(S) & (PbF)
Lead Definitions
Symbol Description
V
CC
COM
V
IN+
V
B
V
S
PO
OC
N.C.
Low side and logic supply voltage
Low side logic ground
Positive sense input
High side supply
High side return
Digital PWM output
Overcurrent output (negative logic)
No connection
Lead Assignment
1
VC
C
VIN
+
8
1
VC
C
VIN
+
8
2
PO
Vs
7
2
PO
Vs
7
3
COM
V
B
6
3
COM
V
B
6
4
OC
NC
5
4
OC
NC
5
8 lead SOIC
Also available LEAD-FREE (PbF)
8 lead PDIP
Also available LEAD-FREE (PbF)
IR2175S
IR2175
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5
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