CY7C1423KV18/CY7C1424KV18
36-Mbit DDR II SIO SRAM Two-Word
Burst Architecture
36-Mbit DDR II SIO SRAM Two-Word Burst Architecture
Features
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Configurations
CY7C1423KV18 – 2M × 18
CY7C1424KV18 – 1M × 36
36-Mbit density (2M × 18, 1M × 36)
333 MHz clock for high bandwidth
Two-word burst for reducing address bus frequency
Double data rate (DDR) interfaces (data transferred at
666 MHz) at 333 MHz
Two input clocks (K and K) for precise DDR timing
❐
SRAM uses rising edges only
Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches
Echo clocks (CQ and CQ) simplify data capture in high speed
systems
Synchronous internally self timed writes
DDR II operates with 1.5 cycle read latency when DOFF is
asserted HIGH
Operates similar to DDR I device with 1 cycle read latency when
DOFF is asserted LOW
1.8 V core power supply with HSTL inputs and outputs
Variable drive HSTL output buffers
Expanded HSTL output voltage (1.4 V to V
DD
)
❐
Supports both 1.5 V and 1.8 V IO supply
Available in 165-ball FBGA package (13 × 15 × 1.4 mm)
Offered in both Pb-free and non Pb-free packages
JTAG 1149.1 compatible test access port
Phase locked loop (PLL) for accurate data placement
Functional Description
The CY7C1423KV18, and CY7C1424KV18 are 1.8 V
synchronous pipelined SRAMs, equipped with DDR II SIO
(double data rate separate I/O) architecture. The DDR II SIO
consists of two separate ports: the read port and the write port to
access the memory array. The read port has data outputs to
support read operations and the write port has data inputs to
support write operations. The DDR II SIO has separate data
inputs and data outputs to completely eliminate the need to
“turnaround” the data bus required with common I/O devices.
Access to each port is accomplished through a common address
bus. Addresses for read and write are latched on alternate rising
edges of the input (K) clock. Write data is registered on the rising
edges of both K and K. Read data is driven on the rising edges
of C and C if provided, or on the rising edge of K and K if C/C are
not provided. Each address location is associated with two 18-bit
words in the case of CY7C1423KV18, and two 36-bit words in
the case of CY7C1424KV18 that burst sequentially into or out of
the device.
Asynchronous inputs include an output impedance matching
input (ZQ). Synchronous data outputs are tightly matched to the
two output echo clocks CQ/CQ, eliminating the need to capture
data separately from each individual DDR II SIO SRAM in the
system design. Output data clocks (C/C) enable maximum
system clocking and data synchronization flexibility.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
For a complete list of related documentation, click
here.
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Selection Guide
Description
Maximum operating frequency
Maximum operating current
× 18
× 36
333 MHz
333
490
600
300 MHz
300
460
Not Offered
250 MHz
250
430
490
Unit
MHz
mA
Cypress Semiconductor Corporation
Document Number: 001-57829 Rev. *I
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised November 16, 2016
CY7C1423KV18/CY7C1424KV18
Logic Block Diagram – CY7C1423KV18
D
[17:0]
18
Write Add. Decode
Read Add. Decode
A
(19:0)
20
Address
Register
Write
Data Reg
Write
Data Reg
1M x 18 Array
1M x 18 Array
LD
Control
Logic
R/W
C
C
CQ
K
K
DOFF
R/W
V
REF
LD
BWS
[1:0]
Control
Logic
CLK
Gen.
Read Data Reg.
36
18
18
Reg.
Reg.
Reg. 18
18
CQ
18
Q
[17:0]
Logic Block Diagram – CY7C1424KV18
36
D
[35:0]
Write Add. Decode
Read Add. Decode
A
(18:0)
19
Address
Register
Write
Data Reg
Write
Data Reg
512K x 18 Array
512K x 18 Array
LD
Control
Logic
R/W
C
C
CQ
K
K
DOFF
R/W
V
REF
LD
BWS
[3:0]
Control
Logic
CLK
Gen.
Read Data Reg.
72
36
36
Reg.
Reg.
Reg. 36
36
CQ
36
Q
[35:0]
Document Number: 001-57829 Rev. *I
Page 2 of 31
CY7C1423KV18/CY7C1424KV18
Contents
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 5
Functional Overview ........................................................ 6
Read Operations ......................................................... 6
Write Operations ......................................................... 6
Byte Write Operations ................................................. 7
Single Clock Mode ...................................................... 7
DDR Operation ............................................................ 7
Depth Expansion ......................................................... 7
Programmable Impedance .......................................... 7
Echo Clocks ................................................................ 7
PLL .............................................................................. 7
Application Example ........................................................ 8
Truth Table ........................................................................ 9
Write Cycle Descriptions ................................................. 9
Write Cycle Descriptions ............................................... 10
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 11
Disabling the JTAG Feature ...................................... 11
Test Access Port ....................................................... 11
Performing a TAP Reset ........................................... 11
TAP Registers ........................................................... 11
TAP Instruction Set ................................................... 11
TAP Controller State Diagram ....................................... 13
TAP Controller Block Diagram ...................................... 14
TAP Electrical Characteristics ...................................... 14
TAP AC Switching Characteristics ............................... 15
TAP Timing and Test Conditions .................................. 16
Identification Register Definitions ................................ 17
Scan Register Sizes ....................................................... 17
Instruction Codes ........................................................... 17
Boundary Scan Order .................................................... 18
Power Up Sequence in DDR II SRAM ........................... 19
Power Up Sequence ................................................. 19
PLL Constraints ......................................................... 19
Maximum Ratings ........................................................... 20
Operating Range ............................................................. 20
Neutron Soft Error Immunity ......................................... 20
Electrical Characteristics ............................................... 20
DC Electrical Characteristics ..................................... 20
AC Electrical Characteristics ..................................... 22
Capacitance .................................................................... 22
Thermal Resistance ........................................................ 22
AC Test Loads and Waveforms ..................................... 22
Switching Characteristics .............................................. 23
Switching Waveforms .................................................... 25
Ordering Information ...................................................... 26
Ordering Code Definitions ......................................... 26
Package Diagram ............................................................ 27
Acronyms ........................................................................ 28
Document Conventions ................................................. 28
Units of Measure ....................................................... 28
Document History Page ................................................. 29
Sales, Solutions, and Legal Information ...................... 31
Worldwide Sales and Design Support ....................... 31
Products .................................................................... 31
PSoC®Solutions ....................................................... 31
Cypress Developer Community ................................. 31
Technical Support ..................................................... 31
Document Number: 001-57829 Rev. *I
Page 3 of 31
CY7C1423KV18/CY7C1424KV18
Pin Configurations
The pin configurations for CY7C1423KV18 and CY7C1424KV18 follow.
[1]
Figure 1. 165-ball FBGA (13 × 15 × 1.4 mm) pinout
CY7C1423KV18 (2M × 18)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
NC/144M
Q9
NC
D11
NC
Q12
D13
V
REF
NC
NC
Q15
NC
D17
NC
TCK
3
A
D9
D10
Q10
Q11
D12
Q13
V
DDQ
D14
Q14
D15
D16
Q16
Q17
A
4
R/W
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
5
BWS
1
NC
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K
K
A
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C
7
NC/288M
BWS
0
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
LD
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
A
10
NC/72M
NC
Q7
NC
D6
NC
NC
V
REF
Q4
D3
NC
Q1
NC
D0
TMS
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
CY7C1424KV18 (1M × 36)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
Q27
D27
D28
Q29
Q30
D30
DOFF
D31
Q32
Q33
D33
D34
Q35
TDO
2
Q18
Q28
D20
D29
Q21
D22
V
REF
Q31
D32
Q24
Q34
D26
D35
TCK
3
D18
D19
Q19
Q20
D21
Q22
V
DDQ
D23
Q23
D24
D25
Q25
Q26
A
4
R/W
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
5
BWS
2
BWS
3
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K
K
A
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C
7
BWS
1
BWS
0
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
LD
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
9
A
D17
D16
Q16
Q15
D14
Q13
V
DDQ
D12
Q12
D11
D10
Q10
Q9
A
10
NC/144M
Q17
Q7
D15
D6
Q14
D13
V
REF
Q4
D3
Q11
Q1
D9
D0
TMS
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
NC/288M NC/72M
Note
1. NC/72M, NC/144M, and NC/288M are not connected to the die and can be tied to any voltage level.
Document Number: 001-57829 Rev. *I
Page 4 of 31
CY7C1423KV18/CY7C1424KV18
Pin Definitions
Pin Name
D
[x:0]
I/O
Pin Description
Input-
Data input signals.
Sampled on the rising edge of K and K clocks during valid write operations.
CY7C1423KV18 - D
[17:0]
synchronous
CY7C1424KV18 - D
[35:0]
Input-
Synchronous load.
This input is brought LOW when a bus cycle sequence is defined. This definition
synchronous includes address and read/write direction. All transactions operate on a burst of 2 data (one clock period
of bus activity).
Input-
Byte write select 0, 1, 2, and 3
active LOW.
Sampled on the rising edge of the K and K clocks during
synchronous write operations. Used to select which byte is written into the device during the current portion of the write
operations. Bytes not written remain unaltered.
CY7C1423KV18 BWS
0
controls D
[8:0]
, BWS
1
controls D
[17:9]
.
CY7C1424KV18BWS
0
controls D
[8:0]
, BWS
1
controls D
[17:9]
,BWS
2
controls D
[26:18]
and BWS
3
controls
D
[35:27].
All the byte write selects are sampled on the same edge as the data. Deselecting a byte write select
ignores the corresponding byte of data and it is not written into the device.
Input-
Address inputs.
Sampled on the rising edge of the K clock during active read and write operations. These
synchronous address inputs are multiplexed for both read and write operations. Internally, the device is organized as
2M × 18 (2 arrays each of 1M × 18) for CY7C1423KV18 and 1M × 36 (2 arrays each of 512K × 36) for
CY7C1424KV18. Therefore, only 20 address inputs are needed to access the entire memory array of
CY7C1423KV18 and 19 address inputs for CY7C1424KV18. These inputs are ignored when the
appropriate port is deselected.
Outputs-
Data output signals.
These pins drive out the requested data during a read operation. Valid data is driven
synchronous out on the rising edge of both the C and C clocks during read operations, or K and K when in single clock
mode. When the read port is deselected, Q
[x:0]
are automatically tristated.
CY7C1423KV18
Q
[17:0]
CY7C1424KV18
Q
[35:0]
Input-
Synchronous read/write input.
When LD is LOW, this input designates the access type (read when
synchronous R/W is HIGH, write when R/W is LOW) for the loaded address. R/W must meet the setup and hold times
around the edge of K.
Input clock
Positive input clock for output data.
C is used in conjunction with C to clock out the read data from the
device. C and C can be used together to deskew the flight times of various devices on the board back to
the controller. See
Application Example on page 8
for further details.
Negative input clock for output data.
C is used in conjunction with C to clock out the read data from
the device. C and C can be used together to deskew the flight times of various devices on the board back
to the controller. See
Application Example on page 8
for further details.
Positive input clock input.
The rising edge of K is used to capture synchronous inputs to the device and
to drive out data through Q
[x:0]
when in single clock mode. All accesses are initiated on the rising edge of K.
Negative input clock input.
K is used to capture synchronous inputs being presented to the device and
to drive out data through Q
[x:0]
when in single clock mode.
CQ referenced with respect to C.
This is a free running clock and is synchronized to the input clock for
output data (C) of the DDR II. In the single clock mode, CQ is generated with respect to K. The timings
for the echo clocks is shown in the
Switching Characteristics on page 23.
CQ referenced with respect to C.
This is a free running clock and is synchronized to the input clock for
output data (C) of the DDR II. In the single clock mode, CQ is generated with respect to K. The timings
for the echo clocks is shown in the
Switching Characteristics on page 23.
Output impedance matching input.
This input is used to tune the device outputs to the system data
bus impedance. CQ, CQ, and Q
[x:0]
output impedance are set to 0.2 × RQ, where RQ is a resistor
connected between ZQ and ground. Alternatively, this pin can be connected directly to V
DDQ
, which
enables the minimum impedance mode. This pin cannot be connected directly to GND or left
unconnected.
LD
BWS
0
,
BWS
1
,
BWS
2
,
BWS
3
A
Q
[x:0]
R/W
C
C
Input clock
K
K
CQ
Input clock
Input clock
Echo clock
CQ
Echo clock
ZQ
Input
Document Number: 001-57829 Rev. *I
Page 5 of 31
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