DATASHEET
LOCO™ PLL CLOCK MULTIPLIER
Description
The ICS501 LOCO
TM
is the most cost effective way to
generate a high-quality, high-frequency clock output from a
lower frequency crystal or clock input. The name LOCO
stands for Low Cost Oscillator, as it is designed to replace
crystal oscillators in most electronic systems. Using
Phase-Locked Loop (PLL) techniques, the device uses a
standard fundamental mode, inexpensive crystal to
produce output clocks up to 160 MHz.
Stored in the chip’s ROM is the ability to generate nine
different multiplication factors, allowing one chip to output
many common frequencies (see table on page 2).
The device also has an output enable pin which tri-states
the clock output when the OE pin is taken low.
This product is intended for clock generation. It has low
output jitter (variation in the output period), but input to
output skew and jitter are not defined or guaranteed. For
applications which require defined input to output skew, use
the ICS570B.
ICS501
Features
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Packaged as 8-pin SOIC, MSOP, or die
•
RoHS 5 (green) or RoHS 6 (green and lead free)
compliant packaging
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IDT’s lowest cost PLL clock
Zero ppm multiplication error
Input crystal frequency of 5 - 27 MHz
Input clock frequency of 2 - 50 MHz
Output clock frequencies up to 160 MHz
Extremely low jitter of 25 ps (one sigma)
Compatible with all popular CPUs
Duty cycle of 45/55 up to 160 MHz
Nine selectable frequencies
Operating voltage of 3.3 V or 5.0 V
Tri-state output for board level testing
25 mA drive capability at TTL levels
Ideal for oscillator replacement
Industrial temperature version available
Advanced, low-power CMOS process
Block Diagram
VDD
S1:0
X1/ICLK
Crystal or
Clock input
X2
2
Crystal
Oscillator
PLL Clock
Multiplier
Circuitry
and ROM
CLK
Optional crystal capacitors
GND
OE
IDT™ / ICS™
LOCO™ PLL CLOCK MULTIPLIER
1
ICS501
REV S 20170331
ICS501
LOCO™ PLL CLOCK MULTIPLIER
CLOCK MULTIPLIER
Pin Assignment
Clock Output Table
S1 S0
0
0
M
1
0
M
1
0
M
1
CLK
4X input
5.3125X input
5X input
6.25X input
2X input
3.125X input
6X input
3X input
8X input
Minimum Input
per page 5
20 MHz
per page 5
4 MHz
per page 5
8 MHz
per page 5
per page 5
per page 5
X1/ I CLK
VDD
GND
S1
1
2
3
4
8
7
6
5
X2
OE
S0
CLK
0
0
M
M
M
1
1
1
8 Pi n ( 150 mi l ) SOI C
0 = connect directly to ground
1 = connect directly to VDD
M = leave unconnected (floating)
Common Output Frequency Examples (MHz)
Output
Input
Selection (S1, S0)
Output
Input
Selection (S1, S0)
20
10
M, M
64
16
0, 0
24
12
M, M
66.66
16.66
0, 0
30
10
1, M
72
12
1, 0
32
16
M, M
75
12
M, 0
33.33
16.66
M, M
80
10
1, 1
37.5
12
M, 1
83.33
16.66
0, 1
40
10
0, 0
90
15
1, 0
48
12
0, 0
100
20
0, 1
50
16.66
1, M
106.25
20
0, M
60
10
1, 0
120
15
1, 1
62.5
20
M, 1
125
20
M, 0
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
Pin
Name
XI/ICLK
VDD
GND
S1
CLK
S0
OE
X2
Pin
Type
Input
Power
Power
Tri-level Iinput
Output
Tri-level Input
Input
Output
Pin Description
Crystal connection or clock input.
Connect to +3.3 V or +5 V.
Connect to ground.
Select 1 for output clock. Connect to GND or VDD or float.
Clock output per table above.
Select 0 for output clock. Connect to GND or VDD or float.
Output enable. Tri-states CLK output when low. Internal pull-up.
Crystal connection. Leave unconnected for clock input.
IDT™ / ICS™
LOCO™ PLL CLOCK MULTIPLIER
2
ICS501
REV S 20170331
ICS501
LOCO™ PLL CLOCK MULTIPLIER
CLOCK MULTIPLIER
External Components
Decoupling Capacitor
As with any high-performance mixed-signal IC, the ICS501
must be isolated from system power supply noise to perform
optimally.
A decoupling capacitor of 0.01µF must be connected
between VDD and the GND. It must be connected close to
the ICS501 to minimize lead inductance. No external power
supply filtering is required for the ICS501.
Crystal Load Capacitors
The total on-chip capacitance is approximately 12 pF. A
parallel resonant, fundamental mode crystal should be
used. The device crystal connections should include pads
for small capacitors from X1 to ground and from X2 to
ground. These capacitors are used to adjust the stray
capacitance of the board to match the nominally required
crystal load capacitance. Because load capacitance can
only be increased in this trimming process, it is important to
keep stray capacitance to a minimum by using very short
PCB traces (and no vias) between the crystal and device.
Crystal capacitors, if needed, must be connected from each
of the pins X1 and X2 to ground.
The value (in pF) of these crystal caps should equal (C
L
-12
pF)*2. In this equation, C
L
= crystal load capacitance in pF.
Example: For a crystal with a 16 pF load capacitance, each
crystal capacitor would be 8 pF [(16-12) x 2 = 8].
Series Termination Resistor
A 33 terminating resistor can be used next to the CLK pin
for trace lengths over one inch.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS501. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these
or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature
Storage Temperature
Soldering Temperature
7V
Rating
-0.5 V to VDD+0.5 V
-40 to +85C
-65 to +150C
260C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature (commercial)
Ambient Operating Temperature (industrial)
Power Supply Voltage (measured in respect to GND)
Min.
0
-40
+3.0
Typ.
Max.
+70
85
+5.25
Units
C
C
V
IDT™ / ICS™
LOCO™ PLL CLOCK MULTIPLIER
3
ICS501
REV S 20170331
ICS501
LOCO™ PLL CLOCK MULTIPLIER
CLOCK MULTIPLIER
DC Electrical Characteristics
VDD=5.0 V ±5%
, Ambient temperature -40 to +85C, unless stated otherwise
Parameter
Operating Voltage
Input High Voltage, ICLK only
Input Low Voltage, ICLK only
Input High Voltage
Input Low Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
IDD Operating Supply Current, 20
Short Circuit Current
On-Chip Pull-up Resistor
Input Capacitance, S1, S0, and OE
Nominal Output Impedance
Symbol
VDD
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
Conditions
ICLK (pin 1)
ICLK (pin 1)
OE (pin 7)
OE (pin 7)
S0, S1
S0, S1
I
OH
= -25 mA
I
OL
= 25 mA
No load, 100M
CLK output
Pin 7
Pins 4, 6, 7
Min.
3.0
(VDD/2)+1
Typ.
Max.
5.25
(VDD/2)-1
Units
V
V
V
V
V
V
V
V
V
mA
mA
k
pF
2.0
0.8
VDD-0.5
0.5
2.4
0.4
20
+70
270
4
20
IDT™ / ICS™
LOCO™ PLL CLOCK MULTIPLIER
4
ICS501
REV S 20170331
ICS501
LOCO™ PLL CLOCK MULTIPLIER
CLOCK MULTIPLIER
AC Electrical Characteristics
VDD = 5.0 V ±5%,
Ambient Temperature -40 to +85 C, unless stated otherwise
Parameter
Input Frequency, crystal input
Input Frequency, clock input
Output Frequency, VDD = 4.75 to 5.25 V
Output Frequency, VDD = 3.0 to 3.6 V
Output Clock Rise Time
Output Clock Fall Time
Output Clock Duty Cycle
PLL Bandwidth
Output Enable Time, OE high to output
on
Output Disable Time, OE low to tri-state
Absolute Clock Period Jitter
One Sigma Clock Period Jitter
Note 1: Measured with 15 pF load.
Symbol
F
IN
F
IN
F
OUT
F
OUT
t
OR
t
OF
t
OD
Conditions
Min.
5
2
Typ.
Max. Units
27
50
160
140
100
90
MHz
MHz
MHz
MHz
MHz
MHz
ns
ns
55
%
kHz
0C to +70C
-40C to +85C
0C to +70C
-40C to +85C
0.8 to 2.0 V, Note 1
2.0 to 8.0 V, Note 1
1.5 V, up to
160 MHz
13
13
13
13
1
1
45
10
50
50
49-51
ns
ns
ps
ps
t
ja
t
js
Deviation from
mean
+70
25
Thermal Characteristics for 8SOIC
Parameter
Thermal Resistance Junction to
Ambient
Symbol
JA
JA
JA
JC
JT
Conditions
Still air
1 m/s air flow
3 m/s air flow
Still air
Min.
Typ.
150
140
120
40
20
Max. Units
C/W
C/W
C/W
C/W
C/W
Thermal Resistance Junction to Case
Thermal Resistance Junction to Top
of Case
Thermal Characteristics for 8MSOP
Parameter
Thermal Resistance Junction to
Ambient
Thermal Resistance Junction to Case
Symbol
JA
JC
Conditions
Still air
Min.
Typ.
95
48
Max. Units
C/W
C/W
IDT™ / ICS™
LOCO™ PLL CLOCK MULTIPLIER
5
ICS501
REV S 20170331
FPGA/CPLD
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