19-44
; Rev 0; 2/09
EVALUATION KIT AVAILABLE
Low-Jitter Frequency Synthesizer
with Selectable Input Reference
General Description
The MAX3673 is a low-jitter frequency synthesizer that
accepts two reference clock inputs and generates nine
phase-aligned outputs. The device features 40kHz jitter
transfer bandwidth, 0.3ps
RMS
(12kHz to 20MHz) inte-
grated phase jitter, and best-in-class power-supply
noise rejection (PSNR), making it ideal for jitter clean-
up, frequency translation, and clock distribution in wire-
less base-station applications.
The MAX3673 operates from a single +3.3V supply and
typically consumes 400mW. The IC is available in an
8mm x 8mm, 56-pin TQFN package, and operates from
-40°C to +85°C.
Features
♦
Two Reference Clock Inputs: LVPECL
♦
Nine Phase-Aligned Clock Outputs: LVPECL
♦
Input Frequencies: 61.44MHz,122.88MHz,
245.76MHz, 307.2MHz
♦
Output Frequencies: 61.44MHz, 122.88MHz,
153.6MHz, 245.76MHz, 307.2MHz
♦
♦
♦
♦
Low-Jitter Generation: 0.3ps
RMS
(12kHz to 20MHz)
Clock Failure Indicator for Both Reference Clocks
External Feedback Provides Zero-Delay Capability
Low Output Skew: 20ps Typical
MAX3673
Applications
3G Wireless Base Stations
Frequency Translation
Jitter Cleanup
Clock Distribution
Pin Configuration and Typical Application Circuits appear at
end of data sheet.
PART
MAX3673ETN+
Ordering Information
TEMP RANGE
-40°C to +85°C
PIN-PACKAGE
56 TQFN-EP*
+Denotes
a lead(Pb)-free/RoHS-compliant package.
*EP
= Exposed pad.
Functional Diagram
SEL_CLK
DM
C
PLL
0.1μF
C
REG
0.22μF
DA
PLL_BYPASS
OUTA_EN
REFCLK0
0
REFCLK0
REFCLK1
1
REFCLK1
DIV M
PFD
61.44MHz
CP
VCO
2.457GHz
DIV A
1
0
OUTA3
OUTA3
OUTA2
OUTA2
OUTA1
IN0FAIL
IN1FAIL
LOCK
DIV N
POWER-ON
RESET
(POR)
1
DIV B
0
SIGNAL QUALIFIER
AND
LOCK DETECT
OUTA1
OUTA0
OUTA0
OUTB_EN
MR
OUTB4
OUTB4
OUTB3
OUTB3
OUTB2
1
MAX3673
0
OUTB2
OUTB1
OUTB1
OUTB0
OUTB0
FB_SEL
FB_IN
FB_IN
DB
1
Low-Jitter Frequency Synthesizer
with Selectable Input Reference
MAX3673
ABSOLUTE MAXIMUM RATINGS
Supply Voltage Range (V
CC
, VCC_VCO)..............-0.3V to +4.0V
LVPECL Output Current (OUTA[3:0],
OUTA[3 : 0]
, OUTB[4:0],
OUTB[4 : 0]
) .............................-56mA
All Other Pins..............................................-0.3V to (V
CC
+ 0.3V)
Continuous Power Dissipation (T
A
= +70°C)
56-Pin TQFN (derate 47.6mW/°C above 70°C)..........3808mW
Operating Junction Temperature (T
J
)................-55°C to +150°C
Storage Temperature Range .............................-65°C to +160°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
CC
= +3.0V to +3.6V, T
A
= -40°C to +85°C, C
PLL
= 0.1µF, C
REG
= 0.22µF. Typical values are at V
CC
= +3.3V, T
A
= +25°C, unless
otherwise noted.)
PARAMETER
Supply Current
POWER-ON RESET
V
CC
Rising
V
CC
Falling
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Output High Voltage
Output Low Voltage
V
IH
V
IL
I
IH
I
IL
V
OH
V
OL
V
IN
= V
CC
V
IN
= GND
I
OH
= -8mA
I
OL
= +8mA
-75
2.4
0.4
V
CC
-
0.7
V
CC
-
2.0
V
CC
-
1.8
0.15
> 40
> 14
1.5
V
IH
= V
CC
- 0.7V, V
IL
= V
CC
- 2.0V
I
DC
(Notes 3, 4)
-100
8
6
+100
V
CC
-
1.34
1.9
(Note 1)
(Note 1)
2.0
0.8
75
2.55
2.45
V
V
V
V
μA
μA
V
V
SYMBOL
I
CC
CONDITIONS
LVPECL outputs unterminated
MIN
TYP
120
MAX
175
UNITS
mA
LVCMOS/LVTTL INPUTS (MR, SEL_CLK, PLL_BYPASS, FB_SEL)
LVCMOS/LVTTL OUTPUTS (IN0FAIL,
IN1FAIL, LOCK)
LVPECL INPUTS (REFCLK0,
REFCLK0,
REFCLK1,
REFCLK1,
FB_IN,
FB_IN)
(Note 2)
Input High Voltage
Input Low Voltage
Input Bias Voltage
Differential-Input Swing
Differential-Input Impedance
Common-Mode Input Impedance
Input Capacitance
Input Current
Input Inrush Current When Power
is Off (Steady State)
Input Inrush Current Overshoot
When Power is Off
V
IH
V
IL
V
CMI
V
V
V
V
P-P
k
k
pF
μA
mA
mA
I
OVERSHOOT
(Notes 3, 4)
2
_______________________________________________________________________________________
Low-Jitter Frequency Synthesizer
with Selectable Input Reference
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= +3.0V to +3.6V, T
A
= -40°C to +85°C, C
PLL
= 0.1µF, C
REG
= 0.22µF. Typical values are at V
CC
= +3.3V, T
A
= +25°C, unless
otherwise noted.)
PARAMETER
Reference Clock Frequency
Reference Clock Frequency
Tolerance
Reference Clock Duty Cycle
Reference Clock Amplitude
Detection Assert Threshold
V
DT
Differential swing (Notes 5, 6)
SYMBOL
f
REF
-200
40
200
CONDITIONS
MIN
TYP
Table 1
+200
60
MAX
UNITS
MHz
ppm
%
mV
P-P
REFERENCE CLOCK INPUTS (REFCLK0,
REFCLK0,
REFCLK1,
REFCLK1)
MAX3673
LVPECL OUTPUTS (OUTA[3:0], OUTA[3:0], OUTB[4:0], OUTB[4:0]) (Note 7)
Output High Voltage
Output Low Voltage
Differential-Output Swing
Output Current When Disabled
Output Frequency
Output Rise/Fall Time
Output Duty Cycle
Output-to-Output Skew
t
SKEW
f
OUT
t
R
, t
F
20% to 80% (Note 8)
PLL_BYPASS = 0
PLL_BYPASS = 1 (Note 9)
Within output bank
All outputs
150
48
45
20
40
40
0.1
61.44
2.457
Integrated 12kHz to 20MHz (Notes 5, 8)
(Note 10)
0.3
5
1.0
V
O
= V
CC
- 2.0V to V
CC
- 0.7V
Tables
2, 3
500
52
55
V
OH
V
OL
V
CC
-
1.13
V
CC
-
1.85
1.1
V
CC
-
0.98
V
CC
-
1.70
1.45
V
CC
-
0.83
V
CC
-
1.55
1.8
130
V
V
V
P-P
μA
MHz
ps
%
ps
OTHER AC ELECTRICAL SPECIFICATIONS
PLL Jitter Transfer Bandwidth
Jitter Peaking
PFD Compare Frequency
VCO Center Frequency
Random Jitter Generation
Determinisitic Jitter Caused by
Power-Supply Noise
Frequency Difference Between
Reference Clock and VCO
Within Which the PLL is
Considered in Lock
Frequency Difference Between
Reference Clock and VCO at
Which the PLL is Considered
Out-of-Lock
PLL Lock Time
t
LOCK
Figure 2
kHz
dB
MHz
GHz
ps
RMS
ps
P-P
500
ppm
800
ppm
600
μs
_______________________________________________________________________________________
3
Low-Jitter Frequency Synthesizer
with Selectable Input Reference
MAX3673
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= +3.0V to +3.6V, T
A
= -40°C to +85°C, C
PLL
= 0.1µF, C
REG
= 0.22µF. Typical values are at V
CC
= +3.3V, T
A
= +25°C, unless
otherwise noted.)
PARAMETER
Master Reset (MR) Minimum
Pulse Width
Propagation Delay from Input to
FB_IN
Propagation Delay from Input to
Any Output
FB_SEL = 1 (Notes 8, 11)
PLL_BYPASS = 1
-120
1.0
SYMBOL
CONDITIONS
MIN
TYP
100
+120
MAX
UNITS
ns
ps
ns
During the power-on-reset time, the LVPECL outputs are held to logic-low (OUTxx = low,
OUTxx
= high). See the
Power-
On-Reset (POR)
section for more information.
Note 2:
LVPECL inputs can be AC- or DC-coupled.
Note 3:
For hot-pluggable purposes, the device can receive LVPECL inputs when no supply voltage is applied. Measured with
V
CC
pins connected to GND. See Figure 1.
Note 4:
Measured with LVPECL input (V
IH
, V
IL
) as specified.
Note 5:
Measured using reference clock input with 550ps rise/fall time (20% to 80%).
Note 6:
When input differential swing is below the specified threshold, a clock failure is declared. See Figure 4.
Note 7:
LVPECL outputs terminated 50Ω to V
TT
= V
CC
- 2V.
Note 8:
Guaranteed by design and characterization.
Note 9:
Measured with 50% duty cycle at reference clock input.
Note 10:
Measured with 50mV
P-P
sinusoidal noise on the power supply, f
NOISE
= 100kHz.
Note 11:
Measured with f
REFCLKx
= f
FB_IN
and matched slew rates.
Note 1:
4
_______________________________________________________________________________________
Low-Jitter Frequency Synthesizer
with Selectable Input Reference
MAX3673
INRUSH CURRENT
(mA)
I
OVERSHOOT
I
DC
t
Figure 1. LVPECL Input Inrush Current
V
CC
POWER-ON-RESET (~ 20μs)
REFCLK0
REFCLK1
OUTxx
IN0FAIL
HIGH
IN1FAIL
HIGH
LOCK
t
LOCK
(~ 600μs)
PLL LOCKED TO REFCLK0
SEL_CLK
LOW
Figure 2. Power-Up, PLL Locks to REFCLK0
_______________________________________________________________________________________
5
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