NB4N121K
3.3V Differential 1:21
Differential Fanout Clock
Driver with HCSL level
Output
Description
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The NB4N121K is a Clock differential input fanout distribution 1 to
21 HCSL level differential outputs, optimized for ultra low
propagation delay variation. The NB4N121K is designed with HCSL
clock distribution for FBDIMM applications in mind.
Inputs can accept differential LVPECL, CML, or LVDS levels.
Single−ended LVPECL, CML, LVCMOS or LVTTL levels are
accepted with the proper V
REFAC
supply (see Figures 5, 10, 11, 12,
and 13). Clock input pins incorporate an internal 50
W
on die
termination resistors.
Output drive current at I
REF
(Pin 1) for 1X load is selected by
connecting to GND. To drive a 2X load, connect I
REF
to V
CC
. See
Figure 9.
The NB4N121K specifically guarantees low output–to–output
skews. Optimal design, layout, and processing minimize skew within
a device and from device to device. System designers can take
advantage of the NB4N121K’s performance to distribute low skew
clocks across the backplane or the motherboard.
Features
QFN−52
MN SUFFIX
CASE 485M
1
52
MARKING DIAGRAM*
52
1
NB4N
121K
AWLYYWWG
•
Typical Input Clock Frequency 100, 133, 166, 200, 266, 333 and
•
•
•
•
•
•
•
400 MHz
340 ps Typical Rise and Fall Times
800 ps Typical Propagation Delay
Dtpd
100 ps Maximum Propagation Delay Variation Per Each
Differential Pair
Additive Phase RMS Jitter: 1 ps Max
Operating Range: V
CC
= 3.0 V to 3.6 V with V
EE
= 0 V
Differential HCSL Output Level (700 mV Peak−to−Peak)
Pb−Free Packages are Available
A
WL
YY
WW
G
= Assembly Site
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
Q0
VTCLK
Q0
Q1
Q1
CLK
CLK
Q19
Q19
VTCLK
V
CC
GND
R
REF
I
REF
Q20
Q20
Figure 1. Pin Configuration
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the
package dimensions section on page 8 of this data sheet.
©
Semiconductor Components Industries, LLC, 2012
April, 2012
−
Rev. 6
1
Publication Order Number:
NB4N121K/D
NB4N121K
VCC
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
Q5
Q0
Q5
Exposed Pad (EP)
52
51
50
49
48
47
46
45
44
43
42
41
40
I
REF
GND
VTCLK
CLK
CLK
VTCLK
V
CC
Q20
Q20
Q19
Q19
Q18
Q18
1
2
3
4
5
6
7
8
9
10
11
12
13
39
38
37
36
35
34
VCC
Q6
Q6
Q7
Q7
Q8
Q8
Q9
Q9
Q10
Q10
Q11
Q11
NB4N121K
33
32
31
30
29
28
27
14
15
16
17
18
19
20
21
22
23
24
25
Q12
Figure 2. Pinout Configuration
(Top View)
Table 1. PIN DESCRIPTION
Pin
1
Name
I
REF
I/O
Output
Description
Output current programming pin to select load drive. For 1X
configuration, connect I
REF
to GND, or for 2X configuration, connect
I
REF
to V
CC
(See Figure 9).
Supply Ground. GND pin must be externally connected to power supply
to guarantee proper operation.
Internal 50
W
Termination Resistor connection Pins. In the differential
configuration when the input termination pins are connected to the com-
mon termination voltage, and if no signal is applied then the device may
be susceptible to self−oscillation.
CLOCK Input (TRUE)
CLOCK Input (INVERT)
Positive Supply pins. V
CC
pins must be externally connected to a power
supply to guarantee proper operation.
Output (INVERT)
2
3, 6
GND
VTCLK,
VTCLK
−
−
4
5
7, 26, 39, 52
8, 10, 12, 14, 16, 18, 20, 22,
24, 27, 29, 31, 33, 35, 37, 40,
42, 44, 46, 48, 50
9, 11, 13, 15, 17, 19, 21, 23,
25, 28, 30, 32, 34, 36, 38, 41,
43, 45, 47, 49, 51
Exposed Pad
CLK
CLK
V
CC
Q[20−0]
LVPECL Input
LVPECL Input
−
HCSL Output
Q[20−0]
HCSL Output
Output (TRUE)
EP
GND
Exposed Pad. The thermally exposed pad (EP) on package bottom (see
case drawing) must be attached to a sufficient heat−sinking conduit for
proper thermal operation. (Note 1)
1. The exposed pad must be connected to the circuit board ground.
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2
VCC
Q17
Q17
Q16
Q16
Q15
Q15
Q14
Q14
Q13
Q13
Q12
26
NB4N121K
Table 2. ATTRIBUTES
Characteristic
Input Default State Resistors
ESD Protection
Moisture Sensitivity (Note 2)
Flammability Rating Oxygen Index: 28 to 34
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
2. For additional information, see Application Note AND8003/D.
Human Body Model
Machine Model
QFN−52
Value
None
>2 kV
400 V
Level 1
UL 94 V−0 @ 0.125 in
622
Table 3. MAXIMUM RATINGS
(Note 3)
Symbol
V
CC
V
I
V
INPP
I
OUT
T
A
T
stg
q
JA
q
JC
T
sol
Parameter
Positive Power Supply
Positive Input
Differential Input Voltage
Output Current
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient) (Note 3)
Thermal Resistance (Junction−to−Case)
Wave Solder
Pb−Free
0 lfpm
500 lfpm
2S2P (Note 4)
QFN−52
QFN−52
QFN−52
|CLK
−
CLKb|
Continuous
Surge
QFN−52
Condition 1
GND = 0 V
GND = 0 V
Condition 2
Rating
4.6
GND
−
0.3
v
V
I
v
V
CC
V
CC
50
100
−40
to +70
−65
to +150
25
19.6
21
265
Unit
V
V
V
mA
mA
°C
°C
°C/W
°C/W
°C/W
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
3. JEDEC standard 51−6, multilayer board
−
2S2P (2 signal, 2 power).
4. JEDEC standard multilayer board
−
2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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3
NB4N121K
Table 4. DC CHARACTERISTICS
(V
CC
= 3.0 V to 3.6 V, T
A
=
−40°C
to +70°C Note 5)
Symbol
I
GND
I
CC
I
IH
I
IL
V
th
V
IH
V
IL
V
IHD
V
ILD
V
ID
V
CMR
V
OH
V
OL
Characteristic
GND Supply Current (All Outputs Loaded)
Power Supply Current (All Outputs Loaded)
Input HIGH Current CLKx, CLKx
Input LOW Current CLKx, CLKx
−150
1X
2X
Min
70
Typ
98
420
780
2.0
−2.0
150
Max
120
Unit
mA
mA
mA
mA
DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED
(Figures 5 and 7)
Input Threshold Reference Voltage Range (Note 6)
Single−Ended Input HIGH Voltage
Single−Ended Input LOW Voltage
1050
V
th
+ 150
GND
V
CC
−
150
V
CC
V
th
−
150
V
CC
V
CC
−
75
2400
V
CC
−
75
740
0
900
150
mV
mV
mV
mV
mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY
(Figures 6 and 8)
Differential Input HIGH Voltage
Differential Input LOW Voltage
Differential Input Voltage (V
IHD
−
V
ILD
)
Input Common Mode Range
1200
GND
75
1163
mV
mV
mV
HCSL OUTPUTS
(Figure 4)
Output HIGH Voltage
Output LOW Voltage
600
−150
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Input parameters vary 1:1 with V
CC
. Measurements taken with outputs in either 1X (all outputs loaded 50
W
to GND) or 2X (all outputs loaded
25
W
to GND) configuration, see Figure 9. For 1X configuration, connect
IREF
to GND, or for 2X configuration, connect
IREF
to V
CC
.
6. V
th
is applied to the complementary input when operating in single ended mode.
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NB4N121K
Table 5. AC CHARACTERISTICS
V
CC
= 3.0 V to 3.6 V, GND = 0 V;
−40°C
to +70°C (Note 7)
Symbol
V
OUTPP
Characteristic
Output Voltage Amplitude (@ V
INPPmin
)
f
in
= 133 MHz
f
in
= 166 MHz
f
in
= 200 MHz
CLK/CLK to Qx/Qx
550
Min
Typ
725
725
725
800
Max
900
900
900
950
100
20
50
80
150
1
250
550
150
Qx, Qx
Qx, Qx
1X
2X
125
150
175
340
700
Unit
mV
t
PLH
,
t
PHL
Dt
PLH
,
Dt
PHL
t
SKEW
Propagation Delay to (See Figure 3)
ps
ps
ps
ps
ps
ps
ps
mV
mV
ps
ps
Propagation Delay Variations Variation Per Each Diff Pair CLK/CLK to Qx/Qx
(Note 8) (See Figure 3)
Duty Cycle Skew (Note 9)
Within−Device Skew, 1X Mode Only (Note 10)
Within−Device Skew, 2X Mode (Note 10)
Device−to−Device Skew (Note 10)
Additive RMS Phase RMS (Note 11) f
in
=133 MHz to 200 MHz
Absolute Crossing Magnitude Voltage
Variation in Magnitude of V
cross
Absolute Magnitude in Output Risetime and Falltime
(From 175 mV to 525 mV)
Variation in Magnitude of Risetime and Falltime (Single−Ended)
(See Figure 4)
t
jit(f)
V
cross
DV
cross
t
r
, t
f
Dt
r,
Dt
f
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
7. Measured by forcing V
INPP
(MIN) from a 50% duty cycle clock source. Measurements taken with outputs in either 1X (all outputs loaded
50
W
to GND) or 2X (all outputs loaded 25
W
to GND) configuration, see Figure 9. For 1X configuration, connect I
REF
to GND, or for 2X
configuration, connect I
REF
to V
CC
. Typical gain is 20 dB.
8. Measured from the input pair crosspoint to each single output pair crosspoint across temp and voltage ranges.
9. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw− and Tpw+.
10. Skew is measured between outputs under identical transition @ 133 MHz.
11. Additive RMS jitter with 50% duty cycle clock signal using phase noise integrated from 12 KHz to 33 MHz
CLK
V
INPP
= V
IH
(CLK)
−
V
IL
(CLK)
= V
IH
(CLK)
−
V
IL
(CLK)
CLK
t
PLH
Q
V
OUTPP
= V
OH
(Q)
−
V
OL
(Q)
= V
OH
(Q)
−
V
OL
(Q)
Q
t
PHL
Dt
PLH
Dt
PHL
Figure 3. AC Reference Measurement
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