FemtoClock® NG
Crystal-to-LVCMOS/LVTTL Clock
840N022
DATA SHEET
General Description
The 840N022 is a LVCMOS/LVTTL clock synthesizer designed for
Ethernet applications. The device generates a selectable 125MHz or
62.5MHz clock signal with excellent phase jitter performance. The
device uses IDT’s fourth generation FemtoClock® NG technology
for an optimum of high clock frequency, low phase noise
performance and low power consumption.The device supports 2.5V
or 3.3V voltage supply and is packaged in a small, lead-free (RoHS
6) 8-lead TSSOP package. The extended temperature range
supports wireless infrastructure, telecommunication, and networking
end equipment requirements.
Features
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Fourth generation FemtoClock® NG technology
125MHz output clock synthesized from a 25MHz fundamental
mode crystal
One LVCMOS/LVTTL clock output
Crystal interface designed for a 12pF parallel resonant crystal
RMS phase jitter @ 125MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.148ps (maximum)
RMS phase jitter @ 125MHz, using a 25MHz crystal
(12kHz - 20MHz): 0.479ps (maximum)
LVCMOS interface levels for the control inputs
Full 2.5V or 3.3V supply voltage
Lead-free (RoHS 6) packaging
-40°C to 85°C ambient operating temperature
Use replacement part: 840N202CKI-dddLF
FREQ_SEL Frequency Table
Input
FREQ_SEL
0 (default)
1
Output Frequency
f
XTAL
= 25MHz
125MHz
62.5MHz
f
XTAL
= 20MHz
100MHz
50MHz
NOTE: FREQ_SEL is an asynchronous control.
OE Function Table
Input
OE
0
1 (default)
Output Enable
Output Q is disabled in high-impedance state
Output Q is enabled.
NOTE: OE is an asynchronous control.
Block Diagram
XTAL_IN
OSC
XTAL_OUT
PFD
&
LPF
FemtoClock
®
NG
VCO
490-637.5MHz
÷5,
÷10
Q
Pin Assignment
VDDA
OE
XTAL_OUT
XTAL_IN
1
2
3
8
7
6
5
VDD
Q
GND
FREQ_SEL
4
÷25
FREQ_SEL
OE
Pulldown
Pullup
840N022
8-lead TSSOP
4.40mm x 3.0mm x 0.925mm
package body
G Package
Top View
840N022 REVISION A 8/14/15
1
©2015 Integrated Device Technology, Inc.
840N022 DATA SHEET
Pin Descriptions and Characteristics
Table 1. Pin Descriptions
Number
1
2
3,
4
5
6
7
8
Name
V
DDA
OE
XTAL_OUT,
XTAL_IN
FREQ_SEL
GND
Q
V
DD
Power
Input
Input
Input
Power
Output
Power
Pulldown
Pullup
Type
Description
Analog power supply.
Output enable pin. LVCMOS interface levels.
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
Frequency select pin. LVCMOS interface levels.
Power supply ground.
Single-ended clock output. LVCMOS/LVTTL interface levels.
Core supply pin.
NOTE:
Pulldown
and
Pullup
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
C
PD
R
Pullup
R
Pulldown
R
OUT
Parameter
Input Capacitance
Power Dissipation
Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
V
DD
= 3.3V
V
DD
= 2.5V
Test Conditions
OE, FREQ_SEL
V
DD
= 3.465V
V
DD
= 2.625V
Minimum
Typical
3.5
11
9
51
51
15
19
Maximum
Units
pF
pF
pF
k
k
FEMTOCLOCK® NG CRYSTAL-TO-LVCMOS/LVTTL CLOCK
SYNTHESIZER
2
REVISION A 8/14/15
840N022 DATA SHEET
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics or AC
Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
XTAL_IN
Other Inputs
Outputs, V
O
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
3.63V
0V to 2V
-0.5V to V
DD
+ 0.5V
-0.5V to V
DD
+ 0.5V
117°C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 3A. Power Supply DC Characteristics,
V
DD
= 3.3V±5% or 2.5V±5%, T
A
= -40°C to 85°C
Symbol
V
DD
V
DDA
I
DDA
I
DD
Parameter
Core Supply Voltage
Analog Supply Voltage
Analog Supply Current
Power Supply Current
Test Conditions
Minimum
2.375
V
DD
– 0.18
Typical
3.3
3.3
Maximum
3.465
V
DD
18
67
Units
V
V
mA
mA
Table 3B. LVCMOS/LVTTL DC Characteristics,
V
DD
= 3.3V±5% or 2.5V±5%, T
A
= -40°C to 85°C
Symbol
V
IH
Parameter
Input High Voltage
OE
FREQ_SEL
V
IL
Input Low Voltage
OE
FREQ_SEL
OE
I
IH
Input High Current
FREQ_SEL
OE
I
IL
Input Low Current
FREQ_SEL
Output High
Voltage; NOTE 1
Output Low Voltage;
NOTE 1
Q
Test Conditions
V
DD
= 3.3V
V
DD
= 2.5V
V
DD
= 3.3V
V
DD
= 3.3V
V
DD
= 2.5V
V
DD
= 2.5V
V
DD
= V
IN
= 3.465V or 2.625V
V
DD
= V
IN
= 3.465V or 2.625V
V
DD
= 3.465V or 2.625V, V
IN
= 0V
V
DD
= 3.465V or 2.625V, V
IN
= 0V
V
DD
= 3.465V
V
DD
= 2.625V
Q
V
DD
= 3.465V or 2.625V
-150
-5
2.6
1.8
0.5
Minimum
2
1.7
-0.3
-0.3
-0.3
-0.3
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
0.5
0.7
0.5
5
150
Units
V
V
V
V
V
V
µA
µA
µA
µA
V
V
V
V
OH
V
OL
NOTE 1: Output terminated with 50 to V
DD
/ 2. See Parameter Measurement Information Section,
LVCMOS Output Load Test Circuit Diagrams.
REVISION A 8/14/15
3
FEMTOCLOCK® NG CRYSTAL-TO-LVCMOS/LVTTL CLOCK
SYNTHESIZER
840N022 DATA SHEET
Table 4. Crystal Characteristics
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Capacitive Load (C
L
)
12
19.60
Test Conditions
Minimum
Typical
Fundamental
25
25.50
80
7
MHz
pF
pF
Maximum
Units
AC Characteristics
Table 5. AC Characteristics,
V
DD
= 3.3V±5% or 2.5V±5%, T
A
= -40°C to 85°C
Symbol
f
OUT
Parameter
Output Frequency
Test Conditions
FREQ_SEL = 0
FREQ_SEL = 1
f
OUT
= 125MHz, 25MHz Crystal,
Integration Range:
1.875MHz – 20MHz
f
OUT
= 125MHz, 25MHz Crystal,
Integration Range:
12kHz – 20MHz
125MHz, Offset: 10Hz
125MHz, Offset: 100Hz
125MHz, Offset: 1kHz
N
Single-Side Band Noise Power
125MHz, Offset: 10kHz
125MHz, Offset: 100kHz
125MHz, Offset: 1MHz
125MHz, Offset: 10MHz
t
R
/ t
F
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
200
48
Minimum
98.00
49.00
Typical
125
62.5
0.104
Maximum
127.50
63.75
0.148
Units
MHz
MHz
ps
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 1
0.286
-51.7
-83.6
-115.9
-130.2
-134.7
-141.8
-158.3
0.479
ps
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
600
52
ps
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE: Characterized with 20MHz and 25MHz crystals.
NOTE 1: Please refer to the phase noise plots.
FEMTOCLOCK® NG CRYSTAL-TO-LVCMOS/LVTTL CLOCK
SYNTHESIZER
4
REVISION A 8/14/15
840N022 DATA SHEET
Typical Phase Noise at 125MHz
Noise Power(dBc/Hz)
Offset Frequency (Hz)
Typical Phase Noise at 125MHz
Noise Power(dBc/Hz)
REVISION A 8/14/15
Offset Frequency (Hz)
5
FEMTOCLOCK® NG CRYSTAL-TO-LVCMOS/LVTTL CLOCK
SYNTHESIZER
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