19-2727; Rev 2; 6/04
KIT
ATION
EVALU
BLE
AVAILA
1.5Gbps Serial ATA-Compatible Mux/Buffer with
Loopback and Equalization
General Description
The MAX3786 is an AC-coupled, serial-ATA (SATA)-
compatible, 1.5Gbps multiplexer/buffer (mux/buffer) IC
that provides the capability to switch a single serial
data signal between two redundant I/O channels.
SATA out-of-band (OOB) signaling is supported using
loss-of-signal (LOS) detect on all three inputs and
shutdown on the corresponding outputs. The high-speed
inputs and outputs are all internally terminated, compati-
ble with 100Ω differential systems, and must be AC-cou-
pled to the controller IC and SATA-compatible disk drive.
Receive equalization (EQ) and transmit preemphasis
(PE) are provided on the dual I/O channels to mitigate
the effects of intersymbol interference in the signal
path. Loopback can be enabled on the nonselected
I/O channel.
The MAX3786 operates from a single +3.3V supply and
typically consumes 520mW with PE and EQ enabled. It
is available in a 5mm x 5mm, 32-lead thin QFN
exposed-pad package and operates over a 0°C to
+85°C temperature range.
Features
♦
< 50ps
P-P
Total Residual Jitter (20in FR-4, EQ
and PE On)
♦
Supports SATA OOB Signaling
♦
Loopback of Nonselected Channel
♦
Receive Equalization and Transmit Preemphasis
on Controller-Side I/O Channels
♦
0°C to +85°C Operation
♦
32-Pin, 5mm
✕
5mm Thin QFN Package
♦
+3.3V Power Supply
MAX3786
Ordering Information
PART
MAX3786UTJ
MAX3786UTJ+
TEMP RANGE PIN-PACKAGE PKG CODE
0°C to +85°C
0°C to +85°C
32 Thin QFN-EP*
(5mm
×
5mm)
32 Thin QFN-EP*
(5mm
×
5mm)
T3255-2
—
Applications
1.5Gbps Serial ATA Redundancy
+Denotes
lead-free package.
*EP
= Exposed pad.
Typical Application Circuit
CONNECTOR
CONNECTOR
2in TO 24in FR-4
CONTROLLER 1
OUT1
IN1
RX
SATA
CONNECTOR
SATA
CONNECTOR
DISK DRIVE
MAX3786
TX
OUT0
CONNECTOR
CONNECTOR
IN0
2in TO 24in FR-4
CONTROLLER 2
Pin Configuration and Functional Diagram appear at end of data sheet.
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1.5Gbps Serial ATA-Compatible Mux/Buffer with
Loopback and Equalization
MAX3786
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
CC
...................................……...-0.5V to +5.0V
Continuous Current at Outputs
(TX±, OUT1±, OUT0±)............................………………±22mA
Input Voltage
(RX±, IN1±, IN0±) ..................................-0.5V to (V
CC
+ 0.5V)
Differential Input Voltage
(RX±, IN1±, IN0±) ...................................………………..±2.0V
Voltage at
PE1EN, PE0EN, EQ1EN, EQ0EN,
LB_EN,
SEL, CM1, CM0 .........................-0.5V to (V
CC
+ 0.5V)
Continuous Power Dissipation (T
A
= +85°C)
32-Pin Thin QFN (derate 21.3mW/°C above +85°C) .1384mW
Operating Temperature Range ....................………0°C to +85°C
Storage Temperature Range .......................…..-55°C to +150°C
Lead Temperature (soldering, 10s) .............……………..+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
CC
= +3.0V to +3.6V, T
A
= 0°C to +85°C. Typical values at V
CC
= +3.3V, T
A
= +25°C, unless otherwise noted.)
PARAMETER
Supply Current
Maximum Data Rate
Differential Input Voltage
(RX, IN1, IN0)
Input Termination
Input Return Loss
Input Equalization
Differential Output Voltage
(TX, OUT0, OUT1) (Note 2)
Output Termination
Output Transition Time
Output Preemphasis
Output Jitter
Total Residual Jitter
Differential Output Skew
LOS Detector Threshold
Output Startup/Shutdown Time
LVCMOS Input High Voltage
V
IH
(Note 7)
1.5
|S11|
SYMBOL
I
CC
EQ and PE off
EQ and PE on
(Note 1)
(Note 2)
Differential
100MHz to 2.5GHz
At 750MHz
PE off
Output disabled by OOB signaling
Single ended to V
CC
1.5Gbps data, 20% to 80% (Notes 1, 3)
At 750MHz (Note 4)
DJ + 14RJ, EQ and PE off (Notes 1, 5, 8)
DJ + 14RJ, EQ and PE on (Notes 1, 6, 8)
(Note 1)
50
42.5
135
50
200
4.5
30
40
40
50
20
150
5
400
1.5
250
85
100
14
4.5
500
600
30
57.5
270
600
115
CONDITIONS
MIN
TYP
125
158
MAX
150
220
UNITS
mA
Gbps
mV
P-P
Ω
dB
dB
mV
P-P
Ω
ps
dB
ps
P-P
ps
P-P
ps
mV
P-P
ns
V
2
_______________________________________________________________________________________
1.5Gbps Serial ATA-Compatible Mux/Buffer with
Loopback and Equalization
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= +3.0V to +3.6V, T
A
= 0°C to +85°C. Typical values at V
CC
= +3.3V, T
A
= +25°C, unless otherwise noted.)
PARAMETER
LVCMOS Input Low Voltage
LVCMOS Input High Current
LVCMOS Input Low Current
SYMBOL
V
IL
I
OH
I
OL
V
IH
= +2.0V to (V
CC
+ 0.3V)
V
IL
= -0.3V to +0.8V
CONDITIONS
MIN
TYP
MAX
0.5
150
150
UNITS
V
µA
µA
MAX3786
AC specifications are guaranteed by design and characterization.
Differential voltage is defined as V
P-P
= (V+ - V-). Inputs and outputs must be AC-coupled for proper operation.
Output transition time measured using a 0000011111 pattern, with transmit PE off.
Transmit PE compensates for 20in of 6-mil-wide differential stripline in FR-4 or equivalent path loss.
Jitter after paths from RX to OUT_ or IN_ to TX. Measured with no jitter on the input, using a ±K28.5 pattern, and a path con-
sisting of the MAX3786 alone.
Note 6:
Jitter after EQ for the paths from RX to OUT_ or IN_ to TX. Measured with no jitter on the input, using a ±K28.5 pattern, and a
path consisting of the MAX3786 plus 20in of 6-mil-wide differential stripline in FR-4 on the output.
Note 7:
Total time for LOS to enable/disable the outputs.
Note 8:
Measured with a 100mV sinusoidal common-mode signal in the 2MHz
≤
f
≤
200MHz range.
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Typical Operating Characteristics
(V
CC
= 3.3V, T
A
= +25°C, unless otherwise noted.)
TOTAL RESIDUAL JITTER vs. PATH LENGTH
(FR-4 STRIPLINE AT OUT0,
±K28.5
PATTERN)
MAX3786 toc02
SUPPLY CURRENT vs. TEMPERATURE
280
260
240
220
200
180
160
140
120
100
80
60
40
0
MAX3786 toc01
DIFFERENTIAL INPUT RETURN LOSS
0
-5
-10
70
TOTAL RESIDUAL JITTER (ps
P-P
)
60
50
40
30
20
10
0
CURRENT (mA)
PE AND EQ ON
|S11| (dB)
-15
-20
-25
PE AND EQ OFF
-30
-35
-40
10
20
30
40
50
60
70
80
0
0.5
1.0
1.5
2.0
2.5
0
5
10
15
20
25
30
TEMPERATURE (°C)
FREQUENCY (GHz)
FR-4 LENGTH (in)
_______________________________________________________________________________________
MAX3786 toc03
80
3
1.5Gbps Serial ATA-Compatible Mux/Buffer with
Loopback and Equalization
MAX3786
Typical Operating Characteristics (continued)
(V
CC
= 3.3V, T
A
= +25°C, unless otherwise noted.)
OUTPUT SWING vs. INPUT SWING
(±K28.5 PATTERN)
MAX3786 toc04
600
500
OUTPUT SWING (mV
P-P
)
400
300
200
100
0
0
100
200
300
400
500
600
INPUT SWING (mV
P-P
)
OUTPUT EYE DIAGRAM, RECEIVE EQ ON
(10in FR-4 STRIPLINE
AT IN0,
±K28.5
PATTERN)
MAX3786 toc05
OUTPUT EYE DIAGRAM, TRANSMIT PE ON
(10in FR-4 STRIPLINE
AT OUT0,
±K28.5
PATTERN)
MAX3786 toc06
70mV/div
70mV/div
100ps/div
100ps/div
OUTPUT EYE DIAGRAM, RECEIVE EQ ON
(20in FR-4 STRIPLINE
AT IN0,
±K28.5
PATTERN)
MAX3786 toc07
OUTPUT EYE DIAGRAM, TRANSMIT PE ON
(20in FR-4 STRIPLINE
AT OUT0,
±K28.5
PATTERN)
MAX3786 toc08
70mV/div
70mV/div
100ps/div
100ps/div
4
_______________________________________________________________________________________
1.5Gbps Serial ATA-Compatible Mux/Buffer with
Loopback and Equalization
Pin Description
PIN
1, 4, 8, 15,
17, 20, 21,
24, 26, 30
2
3
5
6
7
9
10
11
12
13
14
16, 25
18
19
22
23
27
28
29
31
32
EP
NAME
V
CC
TX+
TX-
SEL
RX-
RX+
PE1EN
EQ1EN
LB_EN
CM1
IN1-
IN1+
GND
OUT1-
OUT1+
OUT0-
OUT0+
IN0-
IN0+
CM0
EQ0EN
PE0EN
Exposed
pad
+3.3V Supply Voltage
Positive TX Data Output, CML. Serial ATA compatible.
Negative TX Data Output, CML. Serial ATA compatible.
Multiplex Select Control Input, LVCMOS. Set high to connect RX/TX to OUT1/IN1.
Negative RX Data Input, CML. Serial ATA compatible.
Positive RX Data Input, CML. Serial ATA compatible.
Channel 1 Preemphasis Enable Input, LVCMOS. Set low to enable OUT1 PE.
Channel 1 Equalization Enable Input, LVCMOS. Set low to enable IN1 EQ.
Loopback Enable Input, LVCMOS. Set low to loopback data on nonselected channel.
Input 1 Common-Mode Point. Normally not connected; can be connected to V
CC
through 1.0µF
capacitor. See Figure 1.
Negative Channel 1 Data Input, CML. Serial ATA compatible.
Positive Channel 1 Data Input, CML. Serial ATA compatible.
Supply Ground
Negative Channel 1 Data Output, CML. Serial ATA compatible.
Positive Channel 1 Data Output, CML. Serial ATA compatible.
Negative Channel 0 Data Output, CML. Serial ATA compatible.
Positive Channel 0 Data Output, CML. Serial ATA compatible.
Negative Channel 0 Data Input, CML. Serial ATA compatible.
Positive Channel 0 Data Input, CML. Serial ATA compatible.
Input 0 Common-Mode Point. Normally not connected; can be connected to V
CC
through 1.0µF
capacitor. See Figure 1.
Channel 0 Equalization Enable Input, LVCMOS. Set low to enable IN0 EQ.
Channel 0 Preemphasis Enable Input, LVCMOS. Set low to enable OUT0 PE.
Ground. The exposed pad must be soldered to the circuit board ground for proper thermal and
electrical performance.
FUNCTION
MAX3786
Detailed Description
The MAX3786 consists of three multiplexers, I/O buffers,
and LOS-detection circuitry (see the
Functional Diagram).
The buffers on the controller side provide EQ on the
inputs and PE on the outputs.
from redundant controllers. Loopback is provided on
the IN_/OUT_ side and is controlled by the LVCMOS
input
LB_EN.
When
LB_EN
is low, the nonselected
IN_/OUT_ loops back (see Table 1). The SEL and
LB_EN
control lines are internally pulled high through
40kΩ resistors (see the
Functional Diagram).
Mux/Buffer Logic
By means of the LVCMOS input SEL, a SATA-compati-
ble device at TX/RX can be connected to either
IN0/OUT0 or IN1/OUT1. When SEL is low, TX/RX are
connected to IN0/OUT0, and when SEL is high, TX/RX
are connected to IN1/OUT1. Use of the SEL input pro-
vides the ability to operate a single SATA disk drive
Loss-of-Signal Logic
At each high-speed input to the MAX3786, an LOS cir-
cuit is provided. In this circuit, a differential signal of
50mV
P-P
or less is detected as OFF, and a signal of
greater than 150mV
P-P
is detected as ON. The LOS
detectors, in combination with the select logic, control
their associated high-speed output-disable circuits, so
5
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