NB4N316M
3.3 V AnyLevel] Receiver
to CML Driver/Translator
with Input Hysteresis
2.0 GHz Clock / 2.5 Gb/s Data
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The NB4N316M is a differential Clock or Data receiver and will
accept AnyLevel input signals: LVPECL, CML, LVCMOS, LVTTL,
or LVDS. These signals will be translated to CML, operating up to
2.0 GHz or 2.5 Gb/s, respectively. As such, the NB4N316M is ideal
for SONET, GigE, Fiber Channel, Backplane and other Clock or Data
distribution applications. The CML outputs are 16 mA open collector
(see Figure 18) which requires resistor (R
L
) load path to V
TT
termination voltage (see Figure 19). The open collector CML outputs
must be terminated to V
TT
at power up. The differential outputs
produce Current–Mode Logic (CML) compatible levels when the
receiver is loaded with 50
W
or 25
W
loads connected to 1.8 V, 2.5 V
or 3.3 V supplies. This simplifies device interface by eliminating a
need for coupling capacitors.
The NB4N316M features an input threshold hysteresis of
approximately 25 mV, providing increased noise immunity and stability.
The device is offered in a small 8−pin TSSOP package (MSOP−8
compatible). Application notes, models, and support documentation
are available at www.onsemi.com.
Features
MARKING
DIAGRAM*
8
1
TSSOP−8
DT SUFFIX
CASE 948R
8
E316
ALYWG
G
1
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
•
•
•
•
•
•
•
•
•
Maximum Input Clock Frequency > 2.0 GHz
Maximum Input Data Rate > 2.5 Gb/s
Typically 1 ps of RMS Clock Jitter
Typically 10 ps of Data Dependent Jitter
550 ps Typical Propagation Delay
150 ps Typical Rise and Fall Times
Differential CML Outputs
25 mV of Receiver Input Threshold Hysteresis
Operating Range: V
CC
= 3.0 V to 3.6 V with V
EE
= 0 V and
V
TT
= 1.8 V to 3.6 V
•
Functionally Compatible with Existing 2.5 V / 3.3 V LVEL,
LVEP, EP, and SG Devices
•
−40°C to +85°C Ambient Operating Temperature
•
These are Pb−Free Devices*
D
D
Q
Q
Figure 1. Functional Block Diagram
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2016
1
July, 2016 − Rev. 6
Publication Order Number:
NB4N316M/D
NB4N316M
NC
1
8
V
CC
D
2
7
Q
D
3
6
Q
V
BB
4
5
V
EE
Figure 2. Pinout
(Top View)
and Logic Diagram
Table 1. Pin Description
Pin
1
2
3
4
5
6
7
8
Name
NC
D
D
V
BB
V
EE
Q
Q
V
CC
I/O
−
ECL, CML, LVCMOS, LVDS,
LVTTL Input
ECL, CML, LVCMOS, LVDS,
LVTTL Input
−
−
CML Output
CML Output
−
No Connect.
Noninverted Differential Input. (Note 1)
Inverted Differential Input. (Note 1)
Internally Generated Reference Voltage Supply.
Negative Supply Voltage.
Inverted Differential Output. Typically Terminated with 50
W
Resistor to V
TT
.
Noninverted Differential Output. Typically Terminated with 50
W
Resistor to V
TT
.
Positive Supply Voltage.
Description
1. In the differential configuration if no signal is applied on D/D input, then the device will be susceptible to self−oscillation.
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2
NB4N316M
Table 2. ATTRIBUTES
Characteristics
ESD Protection
Moisture Sensitivity (Note 1)
Flammability Rating
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Human Body Model
Machine Model
8−TSSOP
Oxygen Index: 28 to 34
Value
> 1000 V
> 70 V
Level 3
UL 94 V−0 @ 0.125 in
225
Table 3. MAXIMUM RATINGS
Symbol
V
CC
V
EE
V
I
V
O
T
A
T
stg
q
JA
q
JC
T
sol
Parameter
Positive Power Supply
Negative Power Supply
Positive Input
Negative Input
Output Voltage
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient)
(Note 2)
Thermal Resistance (Junction−to−Case)
Wave Solder
0 lfpm
500 lfpm
1S2P (Note 2)
< 3 Sec @ 260°C
TSSOP−8
TSSOP−8
TSSOP−8
Minimum
Maximum
Condition 1
V
EE
= −0.5 V
V
CC
= +0.5 V
V
EE
= 0 V
V
CC
= 0 V
V
I
= V
CC
+0.4 V
V
I
= V
EE
–0.4 V
Condition 2
Rating
4
−4
4
−4
V
EE
+ 600
V
CC
+ 400
−40 to +85
−65 to +150
190
130
41 to 44
265
Unit
V
V
V
V
mV
mV
°C
°C
°C/W
°C/W
°C/W
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. JEDEC standard multilayer board − 1S2P (1 signal, 2 power) with 8 filled thermal vias under exposed pad.
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3
NB4N316M
Table 4. DC CHARACTERISTICS, CLOCK Inputs, CML Outputs
V
CC
= 3.0 V to 3.6 V, V
EE
= 0 V, T
A
= −40°C to +85°C
Symbol
I
CC
Characteristic
Power Supply Current (Inputs and Outputs Open)
Min
Typ
20
Max
30
Unit
mA
R
L
= 50
W,
V
TT
= 3.6 V to 2.5 V
V
OH
V
OL
|V
OD
|
Output HIGH Voltage (Note 3)
Output LOW Voltage (Note 3)
Differential Output Voltage Magnitude
V
TT
− 60
V
TT
− 1100
640
V
TT
− 10
V
TT
− 800
780
V
TT
V
TT
− 640
1000
mV
mV
mV
R
L
= 25
W,
V
TT
= 3.6 V to 2.5 V
$5%
V
OH
V
OL
|V
OD
|
Output HIGH Voltage (Note 3)
Output LOW Voltage (Note 3)
Differential Output Voltage Magnitude
V
TT
− 60
V
TT
− 550
320
V
TT
− 10
V
TT
− 400
390
V
TT
V
TT
− 320
500
mV
mV
mV
R
L
= 50
W,
V
TT
= 1.8 V
$5%
V
OH
V
OL
|V
OD
|
Output HIGH Voltage (Note 3)
Output LOW Voltage (Note 3)
Differential Output Voltage Magnitude
V
TT
− 170
V
TT
− 1100
570
V
TT
− 10
V
TT
− 800
780
V
TT
V
TT
− 640
1000
mV
mV
mV
R
L
= 25
W,
V
TT
= 1.8 V
$5%
V
OH
V
OL
|V
OD
|
Output HIGH Voltage (Note 3)
Output LOW Voltage (Note 3)
Differential Output Voltage Magnitude
V
TT
− 85
V
TT
− 500
285
V
TT
− 10
V
TT
− 400
390
V
TT
V
TT
− 320
500
mV
mV
mV
DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED
(Figures 14 and 16)
V
th
V
IH
V
IL
V
BB
Input Threshold Reference Voltage Range (Note 5)
Single−ended Input HIGH Voltage
Single−ended Input LOW Voltage
Internally Generated Reference Voltage Supply (Loaded with −100
mA)
V
EE
V
th
+ 100
V
EE
− 400
V
CC
− 1500
V
CC
− 1400
V
CC
V
CC
+ 400
V
th
− 100
V
CC
− 1300
mV
mV
mV
mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY
(Figures 15 and 17)
V
IHD
V
ILD
V
CMR
V
ID(HYST)
|V
ID
|
C
IN
Differential Input HIGH Voltage
Differential Input LOW Voltage
Input Common Mode Range (Differential Configuration)
Differential Input Voltage Hysteresis (V
IHD
− V
ILD
)
Differential Input Voltage Magnitude (|V
IHD
− V
ILD
|) (Note 7)
Input Capacitance (Note 7)
100
1.5
V
EE
V
EE
− 400
V
EE
25
V
CC
− V
EE
V
CC
+ 400
V
CC
− 100
V
CC
mV
mV
mV
mV
mV
pF
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
3. CML outputs require R
L
receiver termination resistors to V
TT
for proper operation. Outputs must be connected through R
L
to V
TT
at power
up. The output parameters vary 1:1 with V
TT
. V
TT
= 1.71 V to 3.6 V.
4. Input parameters vary 1:1 with V
CC
.
5. V
th
is applied to the complementary input when operating in single−ended mode.
6. V
CMR
(MIN) varies 1:1 with V
EE
, V
CMR
max varies 1:1 with V
CC
.
7. Parameter guaranteed by design and evaluation but not tested in production.
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NB4N316M
Table 5. AC CHARACTERISTICS
V
CC
= 3.0 V to 3.6 V, V
EE
= 0 V; (Note 8)
−40°C
Symbol
V
OUTPP
Characteristic
Output Voltage Amplitude (R
L
= 50
W)
f
in
≤
1 GHz
(See Figure 12)
f
in
≤
1.5 GHz
f
in
≤
2.0 GHz
Output Voltage Amplitude (R
L
= 25
W)
f
in
≤
1 GHz
(See Figure 12)
f
in
≤
1.5 GHz
f
in
≤
2.0 GHz
Maximum Operating Data Rate
Propagation Delay to Output Differential
@ 0.25 GHz
Duty Cycle Skew (Note 9)
Device to Device Skew (Note 13)
RMS Random Clock Jitter R
L
= 50
W
and
f
in
= 750 MHz
R
L
= 25
W
(Note 11)
f
in
= 1.5 GHz
f
in
= 2.0 GHz
Peak−to−Peak Data Dependent Jitter R
L
= 50
W
f
DATA
= 1.5 Gb/s
(Note 12)
f
DATA
= 2.5 Gb/s
Peak−to−Peak Data Dependent Jitter R
L
= 25
W
f
DATA
= 1.5 Gb/s
(Note 12)
f
DATA
= 2.5 Gb/s
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 10)
Output Rise/Fall Times @ 0.25 GHz
(20% − 80%)
Q, Q
200
150
300
Min
550
400
200
280
280
200
1.5
350
Typ
660
640
400
370
360
300
2.5
550
2
20
1
1
1
15
20
5
10
750
20
100
3
3
3
55
85
35
35
200
150
300
Max
Min
550
400
200
280
280
200
1.5
350
25°C
Typ
660
640
400
370
360
400
2.5
550
2
20
1
1
1
15
20
5
10
750
20
100
3
3
3
55
85
35
35
200
150
300
Max
Min
550
400
200
280
280
200
1.5
350
85°C
Typ
660
640
400
mV
370
360
400
2.5
550
2
20
1
1
1
15
20
5
10
750
20
100
3
3
3
55
85
35
35
mV
ps
Gb/s
ps
ps
ps
Max
Unit
mV
V
OUTPP
f
DATA
t
PLH
,
t
PHL
t
SKEW
t
JITTER
V
INPP
t
r
t
f
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
8. Measured by forcing V
INPP
(MIN) from a 50% duty cycle clock source. All output loaded with an external R
L
= 50
W
and R
L
= 25
W
to V
TT
.
Outputs must be connected through R
L
to V
TT
at power up. Input edge rates 150 ps (20% − 80%).
9. Duty cycle skew is measured between differential outputs using the deviations of the sum of T
pw−
and T
pw+
@ 0.25 GHz.
10. V
INPP
(MAX) cannot exceed V
CC
− V
EE
. Input voltage swing is a single−ended measurement operating in differential mode.
11. Additive RMS jitter with 50% duty cycle clock signal.
12. Additive peak−to−peak data dependent jitter with input NRZ data signal (PRBS 2
23
−1).
13. Device to device skew is measured between outputs under identical transition @ 0.5 GHz.
800
0.8
OUTPUT VOLTAGE AMPLITUDE (mV)
OUTPUT VOLTAGE AMPLITUDE (mV)
700
600
500
400
300
200
100
0
0.5
0.75
1
1.25
1.5
1.75
2
R
L
= 25
W
R
L
= 50
W
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.5
0.75
1
1.25
1.5
1.75
2
R
L
= 25
W
R
L
= 50
W
INPUT CLOCK FREQUENCY (GHz)
(V
CC
− V
EE
= 3.3 V V
TT
= 3.3 V @ 255C V
in
= 100 mV)
INPUT CLOCK FREQUENCY (GHz)
(V
CC
− V
EE
= 3.0 V V
TT
= 1.71 V @255C V
in
= 100 mV)
Figure 3. Output Voltage Amplitude (V
OUTPP
) versus Input Clock Frequency (f
IN
) at Ambient Temperature (Typical)
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