Ordering number : EN6037
CMOS IC
LC72723, LC72723M
RDS Demodulation IC
Overview
The LC72723 is an RDS (Radio Data System) signal
demodulation IC. This IC integrates a bandpass filter, the
demodulation circuit, and buffer RAM on a single chip
and can read out RDS data in slave mode operation with
the provision of an external clock input. It also supports
master mode, in which the data is read out in
synchronization with an RDS clock output provided by the
IC itself.
Package Dimensions
unit: mm
3006B-DIP16
[LC72723]
16
9
7.62
6.4
1
19.2
8
Functions
• Bandpass filter: Switched capacitor filter (SCF)
• RDS demodulation: Functions include 57kHz carrier
regeneration, clock regeneration, biphase decoding, and
differential decoding
• Buffer RAM: Stores 128 bits (about 100 ms) of data.
• Data output: Output can be switched between master
mode and slave mode readout.
• RDS ID detection: Supports ID reset
• Standby control: Stops the crystal oscillator.
• Fully adjustment free.
0.71
2.54
0.48
1.2
3.4
3.65max
3.0
SANYO: DIP16
unit: mm
3035A-MFP16
[LC72723M]
16
9
0.625
Ratings
• Operating supply voltage: 4.5 to 5.5 V
• Operating temperature: –40 to 85°C
• Packages: DIP16 and MFP16
1
10.1
1.5
8
5.15
6.4
4.4
1.8max
0.15
0.35
1.27
0.605
0.1
SANYO: MFP16
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
40299RM (OT) No. 6037-1/8
0.25
LC72723, LC72723M
Pin Assignment (DIP16/MFP16)
Block Diagram
No. 6037-2/8
LC72723, LC72723M
Pin Descriptions
Pin No.
Pin
Function
I/O
Pin circuit type
1
VREF
Reference voltage output (Vdda/2)
Output
2
MPXIN
Base band (multiplex) signal input
Input
5
FLOUT
Subcarrier output (filter output)
Output
6
CIN
Subcarrier input (comparator input)
Input
3
4
8
Vdda
Vssa
XOUT
Analog system power supply (+5 V)
Analog system ground
Crystal element output (4.332 MHz)
—
—
Output
—
—
9
XIN
Crystal element input (or external reference signal input)
7
12
13
TEST
MODE
RST
Test input
Readout mode setting (0: master, 1: slave)
RDS ID and RAM reset (Active high logic)
Input
14
RDDA
RDS data output
Output
15
RDCL
RDS clock output (master mode)
RDS clock input (slave mode)
I/O
16
RDS-ID/READY
RDS ID/ready output (Active low)
Output
11
10
Vddd
Vssd
Digital system power supply (+5 V)
Digital system ground
—
—
—
—
No. 6037-3/8
LC72723, LC72723M
Specifications
Absolute Maximum Ratings
at Ta = 25°C, Vssd = Vssa = 0 V
Parameter
Maximum supply voltage
Symbol
V
DD
max
V
IN
1 max
Maximum input voltage
V
IN
2 max
V
IN
3 max
Vo1 max
Maximum output voltage
Vo2 max
Vo3 max
Maximum output current
Io1 max
Io2 max
Pd max
Topr
Tstg
Vddd, Vdda
*
TEST, MODE, RST
XIN, RDCL
MPXIN, CIN
RDS-ID (READY)
XOUT, RDDA, RDCL
FLOUT
XOUT, FLOUT, RDDA, RDCL
RDS–ID (READY)
(Ta
≤
85°C)
Conditions
Ratings
–0.3 to 7.0
–0.3 to +7.0
–0.3 to Vddd + 0.3
–0.3 to Vdda + 0.3
–0.3 to +7.0
–0.3 to Vddd + 0.3
–0.3 to Vdda + 0.3
+3.0
+20.0
DIP16 : 300
MFP16 : 140
–40 to +85
–55 to +125
Unit
V
V
V
V
V
V
V
mA
mA
mW
mW
°C
°C
Allowable power dissipation
Operating temperature
Storage temperature
*:
Note that Vdda must be less than or equal to Vddd + 0.3 V
Allowable Operating Ranges
at Ta = –40 to +85°C, Vssd = Vssa = 0 V, Vddd = Vdda
Parameter
Supply voltage
High-level input voltage
Low-level input voltage
Output voltage
Symbol
V
DD
V
IH
1
V
IH
2
V
IL
Vo1
Vo2
V
IN
1
Input amplitude
V
IN
2
VX
IN
Guaranteed oscillator operating range
Crystal oscillator frequency deviation
RDCL setup time
RDCL high-level time
RDCL low-level time
Data output time
READY output time
READY low-level time
Xtal
TXtal
t
CS
t
CH
t
CL
t
DC
t
RC
t
RL
Conditions
Vddd, Vdda: Vddd = Vdda
TEST, MODE, RST
RDCL
TEST, MODE, RST, RDCL
RDDA, RDCL
RDS–ID (READY)
f = 57 ±2 KHz
MPXIN
XIN
XIN, XOUT: C1
≤
120
Ω
XIN, XOUT: Fo = 4.332 MHz
RDCL, RDDA
RDCL
RDCL
RDCL, RDDA
RDCL, READY
READY
0
0.75
0.75
0.75
0.75
107
100% modulation, composite
100
400
4.332
±100
1500
Ratings
min
4.5
07 Vddd
0.7 Vddd
0
typ
5.0
max
5.5
6.5
Vddd
0.3 Vddd
Vddd
6.5
50
Unit
V
V
V
V
V
V
mVrms
mVrms
mVrms
MHz
ppm
µs
µs
µs
µS
µs
ms
No. 6037-4/8
LC72723, LC72723M
Electrical Characteristics
at Ta = –40 to +85°C, Vssd = Vssa = 0 V, Vddd = Vdda
Parameter
Symbol
Rmpxin
Rcin
Rf
fc
BW–3dB
Gain
Att1
Stop band attenuation
Att2
Att3
Reference voltage output
Hysteresis
Low-level output voltage
High-level output voltage
High-level input current
Vref
V
HIS
V
OL1
V
OL2
V
OH
I
IH
1
I
IH
2
I
IL
1
I
IL
2
I
OFF
Idd
Conditions
MPXIN-Vssa: f = 57 KHz
CIN-Vssa: f = 57 KHz
XIN
FLOUT
FLOUT
MPXIN-FLOUT: f = 57 KHz
FLOUT:
∆f
= ±7 KHz
FLOUT: f < 45 KHz, f > 70 KHz
FLOUT: f < 20 KHz
Vref: Vdda = 5 V
TEST, MODE, RST, RDCL
RDDA, RDCL : I = 2 mA
RDS-ID (READY): I = 8 mA
RDDA, RDCL : I = 2 mA
TEST, MODE, RST, RDCL : V
I
= 6.5 V
XIN: V
I
= Vddd
TEST, MODE, RST, RDCL : V
I
= 0 V
XIN: V
I
= 0 V
RDS-ID (READY): V
O
= 6.5 V
Vddd + Vdda
8
2.0
2.0
Vddd – 0.4
5.0
11
5.0
11
5.0
56.5
2.5
28
30
40
50
2.5
0.1 Vddd
0.4
0.4
Ratings
min
typ
23
100
1.0
57.0
3.0
31
57.5
3.5
34
max
Unit
KΩ
KΩ
MΩ
KHz
KHz
dB
dB
dB
dB
V
V
V
V
V
µA
µA
µA
µA
µA
mA
Input resistance
Internal feedback resistance
Center frequency
–3dB bandwidth
Gain
Low-level input current
Output off leakage current
Current drain
Inputs and Outputs
TEST
0
0
1
1
MODE
0
1
0
1
Master mode
Slave mode
Standby mode (crystal oscillator stopped)
IC test mode (Cannot be set by users.)
Circuit operating mode
RDCL pin
Clock output
Clock input
—
—
RDS-ID/READY pin
RDS-ID output
READY output
—
—
RST pin
RST = 0
RST = 1
Normal operation
The RDS-ID and demodulation circuits are cleared, and (in slave mode) the READY state and memory are cleared.
RDS ID/READY pin
Master mode RDS-ID output (active low)
Slave mode
Readout data ready output (active low)
Note: The RDS-ID (READY) pin is an n-channel open-drain output, and data is read out by connecting a pull-up resistor.
No. 6037-5/8
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