19-2786; Rev 1; 12/03
3.3V, 16-Bit, 200Msps High Dynamic
Performance DAC with CMOS Inputs
General Description
The MAX5885 is an advanced, 16-bit, 200Msps digital-
to-analog converter (DAC) designed to meet the
demanding performance requirements of signal synthe-
sis applications found in wireless base stations and
other communications applications. Operating from a
single 3.3V supply, this DAC offers exceptional dyna-
mic performance such as 77dBc spurious-free dynamic
range (SFDR) at f
OUT
= 10MHz. The DAC supports
update rates of 200Msps at a power dissipation of less
than 200mW.
The MAX5885 utilizes a current-steering architecture,
which supports a full-scale output current range of 2mA
to 20mA, and allows a differential output voltage swing
between 0.1V
P-P
and 1V
P-P
.
The MAX5885 features an integrated 1.2V bandgap
reference and control amplifier to ensure high accuracy
and low noise performance. Additionally, a separate
reference input pin enables the user to apply an exter-
nal reference source for optimum flexibility and to
improve gain accuracy.
The digital and clock inputs of the MAX5885 are
designed for CMOS-compatible voltage levels. The
MAX5885 is available in a 48-pin QFN package with an
exposed paddle (EP) and is specified for the extended
industrial temperature range (-40°C to +85°C).
Refer to the MAX5883 and MAX5884 data sheets for
pin-compatible 12- and 14-bit versions of the MAX5885.
For LVDS high-speed versions, refer to the MAX5886/
MAX5887/MAX5888 data sheet.
♦
200Msps Output Update Rate
♦
Single 3.3V Supply Operation
♦
Excellent SFDR and IMD Performance
SFDR = 77dBc at f
OUT
= 10MHz (to Nyquist)
IMD = -88dBc at f
OUT
= 10MHz
ACLR = 74dB at f
OUT
= 30.72MHz
♦
2mA to 20mA Full-Scale Output Current
♦
CMOS-Compatible Digital and Clock Inputs
♦
On-Chip 1.2V Bandgap Reference
♦
Low Power Dissipation
♦
48-Pin QFN-EP Package
Features
MAX5885
Ordering Information
PART
MAX5885EGM
TEMP RANGE
-40°C to +85°C
PIN-PACKAGE
48 QFN-EP*
*EP
= Exposed paddle.
Pin Configuration
B5
B6
DV
DD
B9
B10
39
38
48
47
46
B3
B4
45
44
43
42
41
40
Applications
Base Stations: Single/Multicarrier UMTS,
CDMA, GSM
Communications: LMDS, MMDS, Point-to-Point
Microwave
Digital Signal Synthesis
Automated Test Equipment (ATE)
Instrumentation
B1
B0
XOR
VCLK
CLKGND
CLKP
CLKN
CLKGND
VCLK
PD
AV
DD
AGND
1
2
3
4
5
6
7
8
9
10
11
12
37
36
35
34
33
32
31
30
29
28
27
26
25
B11
TOP VIEW
B2
DGND
B7
B8
B12
B13
B14
B15
DGND
DV
DD
SEL0
N.C.
N.C.
N.C.
N.C.
N.C.
MAX5885
13
14
15
16
17
18
19
20
21
22
23
DACREF
N.C.
FSADJ
________________________________________________________________
Maxim Integrated Products
AGND
IOUTN
IOUTP
QFN
AGND
AV
DD
AGND
AV
DD
AGND
REFIO
24
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
3.3V, 16-Bit, 200Msps High Dynamic
Performance DAC with CMOS Inputs
MAX5885
ABSOLUTE MAXIMUM RATINGS
AV
DD
, DV
DD
, VCLK to AGND................................-0.3V to +3.9V
AV
DD
, DV
DD
, VCLK to DGND ...............................-0.3V to +3.9V
AV
DD
, DV
DD
, VCLK to CLKGND ...........................-0.3V to +3.9V
AGND, CLKGND to DGND....................................-0.3V to +0.3V
DACREF, REFIO, FSADJ to AGND.............-0.3V to AV
DD
+ 0.3V
IOUTP, IOUTN to AGND................................-1V to AV
DD
+ 0.3V
CLKP, CLKN to CLKGND...........................-0.3V to VCLK + 0.3V
B0–B15, SEL0, PD, XOR to DGND.............-0.3V to DV
DD
+ 0.3V
Continuous Power Dissipation (T
A
= +70°C)
48-Pin QFN (derate 27mW/°C above +70°C)............2162.2mW
Thermal Resistance (θ
JA
) ..............................................+37°C/W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AV
DD
= DV
DD
= VCLK = 3.3V, AGND = DGND = CLKGND = 0V, external reference, V
REFIO
= 1.25V, R
L
= 50Ω, I
OUT
= 20mA,
f
CLK
= 200Msps, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
≥+25°C
guaranteed by production test, <+25°C guaranteed by design
and characterization. Typical values are at T
A
= +25°C.)
PARAMETER
STATIC PERFORMANCE
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Offset Drift
Full-Scale Gain Error
Gain Drift
Full-Scale Output Current
Min Output Voltage
Max Output Voltage
Output Resistance
Output Capacitance
DYNAMIC PERFORMANCE
Output Update Rate
Noise Spectral Density
Spurious-Free Dynamic Range to
Nyquist
f
CLK
f
CLK
= 100MHz
f
CLK
= 200MHz
SFDR
f
CLK
= 100MHz
f
OUT
= 16MHz, -12dB FS
f
OUT
= 80MHz, -12dB FS
f
OUT
= 1MHz, 0dB FS
f
OUT
= 1MHz, -6dB FS
f
OUT
= 1MHz, -12dB FS
1
-155
-148
88
83
80
dBc
200
Msps
dB FS/
Hz
R
OUT
C
OUT
I
OUT
GE
FS
External reference, T
A
≥
+25°C
Internal reference
External reference
(Note 1)
Single ended
Single ended
2
-0.5
1.1
1
5
-3.5
±100
±50
20
INL
DNL
OS
Measured differentially
Measured differentially
-0.025
16
±0.006
±0.003
±0.003
±50
+1.3
+0.025
Bits
%FS
%FS
%FS
ppm/°C
%FS
ppm/°C
mA
V
V
MΩ
pF
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
2
_______________________________________________________________________________________
3.3V, 16-Bit, 200Msps High Dynamic
Performance DAC with CMOS Inputs
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD
= DV
DD
= VCLK = 3.3V, AGND = DGND = CLKGND = 0V, external reference, V
REFIO
= 1.25V, R
L
= 50Ω, I
OUT
= 20mA,
f
CLK
= 200Msps, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
≥+25°C
guaranteed by production test, <+25°C guaranteed by design
and characterization. Typical values are at T
A
= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
f
CLK
= 100MHz
Spurious-Free Dynamic Range to
Nyquist
f
OUT
= 10MHz, -12dB FS
f
OUT
= 30MHz, -12dB FS
f
OUT
= 10MHz, -12dB FS
SFDR
f
CLK
= 200MHz
f
OUT
= 16MHz, -12dB FS,
T
A
≥+25°C
f
OUT
= 30MHz, -12dB FS
f
OUT
= 50MHz, -12dB FS
f
CLK
= 100MHz
Two-Tone IMD
TTIMD
f
CLK
= 200MHz
Four-Tone IMD, 1MHz Frequency
Spacing, GSM Model
Adjacent Channel Leakage
Power Ratio, 4.1MHz Bandwidth,
WCDMA Model
Output Bandwidth
REFERENCE
Internal Reference Voltage Range
Reference Input Compliance
Range
Reference Input Resistance
Reference Voltage Drift
ANALOG OUTPUT TIMING
Output Fall Time
Output Rise Time
Output Voltage Settling Time
Output Propagation Delay
Glitch Energy
Output Noise
TIMING CHARACTERISTICS
Data to Clock Setup Time
Data to Clock Hold Time
t
SETUP
t
HOLD
Referenced to rising edge of clock (Note 4)
Referenced to rising edge of clock (Note 4)
0.4
1.25
ns
ns
N
OUT
I
OUT
= 2mA
I
OUT
= 20mA
t
FALL
t
RISE
t
SETTLE
t
PD
90% to 10% (Note 3)
10% to 90% (Note 3)
Output settles to 0.025% FS (Note 3)
(Note 3)
375
375
11
1.8
1
30
30
ps
ps
ns
ns
pV-s
pA/√Hz
V
REFIO
V
REFIOCR
R
REFIO
TCO
REF
1.1
0.125
10
±50
1.21
1.34
1.25
V
V
kΩ
ppm/°C
FTIMD
f
CLK
= 150MHz
f
CLK
=
184.32MHz
(Note 2)
f
OUT1
= 9MHz, -6dB FS
f
OUT2
= 10MHz, -6dB FS
f
OUT1
= 29MHz, -6dB FS
f
OUT2
= 30MHz, -6dB FS
f
OUT
= 31.99MHz,
-12dB FS
f
OUT
= 30.72MHz
68
MIN
TYP
77
73
72
76
71
71
-88
dBc
-74
-82
dBc
dBc
MAX
UNITS
MAX5885
ACLR
BW
-1dB
74
450
dB
MHz
_______________________________________________________________________________________
3
3.3V, 16-Bit, 200Msps High Dynamic
Performance DAC with CMOS Inputs
MAX5885
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD
= DV
DD
= VCLK = 3.3V, AGND = DGND = CLKGND = 0V, external reference, V
REFIO
= 1.25V, R
L
= 50Ω, I
OUT
= 20mA,
f
CLK
= 200Msps, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
≥+25°C
guaranteed by production test, <+25°C guaranteed by design
and characterization. Typical values are at T
A
= +25°C.)
PARAMETER
Data Latency
Minimum Clock Pulse Width High
t
CH
CLKP, CLKN
Minimum Clock Pulse Width Low
t
CL
CLKP, CLKN
CMOS LOGIC INPUTS (B0–B15, PD, SEL0, XOR)
Input Logic High
Input Logic Low
Input Leakage Current
Input Capacitance
CLOCK INPUTS (CLKP, CLKN)
Differential Input Voltage Swing
Differential Input Slew Rate
Common-Mode Voltage Range
Input Resistance
Input Capacitance
POWER SUPPLIES
Analog Supply Voltage Range
Digital Supply Voltage Range
Clock Supply Voltage Range
Analog Supply Current
Digital Supply Current
Clock Supply Current
Power Dissipation
Power-Supply Rejection Ratio
AV
DD
DV
DD
V
CLK
I
AVDD
I
DVDD
I
VCLK
P
DISS
PSRR
f
CLK
= 100Msps, f
OUT
= 1MHz
Power-down
f
CLK
= 100Msps, f
OUT
= 1MHz
Power-down
f
CLK
= 100Msps, f
OUT
= 1MHz
Power-down
f
CLK
= 100Msps, f
OUT
= 1MHz
Power-down
AV
DD
= VCLK = DV
DD
= 3.3V
±5%
(Note 5)
-0.1
3.135
3.135
3.135
3.3
3.3
3.3
27
0.3
8.5
10
5.5
10
135
1
+0.1
3.465
3.465
3.465
V
V
V
mA
mA
µA
mA
µA
mW
%FS/V
V
CLK
SR
CLK
V
COM
R
CLK
C
CLK
Sine wave
Square wave
(Note 5)
≥1.5
≥0.5
>100
1.5
±20%
5
5
V
P-P
V/µs
V
kΩ
pF
V
IH
V
IL
I
IN
C
IN
-15
5
0.7 x
DV
DD
0.3 x
DV
DD
+15
SYMBOL
CONDITIONS
MIN
TYP
3.5
1.5
1.5
MAX
UNITS
Clock
cycles
ns
ns
V
V
µA
pF
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Nominal full-scale current I
OUT
= 32
✕
I
REF
.
This parameter does not include update-rate depending effects of sin(x)/x filtering inherent in the MAX5885.
Parameter measured single ended into a 50Ω termination resistor.
Parameter guaranteed by design.
Parameter defined as the change in midscale output caused by a ±5% variation in the nominal supply voltage.
4
_______________________________________________________________________________________
3.3V, 16-Bit, 200Msps High Dynamic
Performance DAC with CMOS Inputs
MAX5885
Typical Operating Characteristics
(AV
DD
= DV
DD
= VCLK = 3.3V, external reference, V
REFIO
= 1.25V, R
L
= 50Ω, I
OUT
= 20mA, T
A
= +25°C, unless otherwise noted.)
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (f
CLK
= 50MHz)
90
80
70
SFDR (dBc)
SFDR (dBc)
60
50
40
30
20
10
0
0
5
10
15
20
25
f
OUT
(MHz)
-6dB FS
0dB FS
-12dB FS
MAX5885 toc01
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (f
CLK
= 100MHz)
MAX5885 toc02
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (f
CLK
= 150MHz)
90
80
70
SFDR (dBc)
60
50
40
30
20
10
0
-6dB FS
0dB FS
-12dB FS
MAX5885 toc03
100
100
90
80
70
60
50
40
30
20
10
0
0
10
20
30
40
0dB FS
-12dB FS
-6dB FS
100
50
0
15
30
45
60
75
f
OUT
(MHz)
f
OUT
(MHz)
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (f
CLK
= 200MHz)
MAX5885 toc04
TWO-TONE IMD vs. OUTPUT FREQUENCY
(1MHz CARRIER SPACING, f
CLK
= 100MHz)
MAX5885 toc05
TWO-TONE INTERMODULATION DISTORTION
(f
CLK
= 100MHz)
-10
-20
OUTPUT POWER (dBm)
-30
-40
-50
-60
-70
-80
-90
2 x f
T1
- f
T2
2 x f
T2
- f
T1
f
T1
f
T2
A
OUT
= -6dB FS
BW = 12MHz
f
T1
= 28.9429MHz
f
T2
= 29.8706MHz
MAX5885 toc06
MAX5885 toc09
100
90
80
70
SFDR (dBc)
60
50
40
30
20
10
0
0
10
20 30 40 50 60 70 80
f
OUT
(MHz)
-6dB FS
0dB FS
-12dB FS
-100
-90
TWO-TONE IMD (dBc)
-80
-70
-6dB FS
-60
-50
-40
-12dB FS
0
-100
0
10
20
30
40
50
24 25 26 27 28 29 30 31 32 33 34 35 36
f
OUT
(MHz)
f
OUT
(MHz)
90 100
TWO-TONE IMD vs. OUTPUT FREQUENCY
(1MHz CARRIER SPACING, f
CLK
= 200MHz)
MAX5885 toc07
SFDR vs. OUTPUT FREQUENCY
(f
CLK
= 200MHz, A
OUT
= -6dB FS)
MAX5885 toc08
SFDR vs. f
OUT
AND TEMPERATURE
(f
CLK
= 200MHz, A
OUT
= -6dB FS, I
FS
= 20mA)
100
90
80
70
SFDR (dBc)
T
A
= -40°C
-100
-90
TWO-TONE IMD (dBc)
-12dB FS
-80
100
I
OUT
= 20mA
80
SFDR (dBc)
60
I
OUT
= 5mA
40
I
OUT
= 10mA
60
50
40
30
T
A
= +85°C
-70
-60
-50
-40
0
10
20
30
40
50
60
70
80
f
OUT
(MHz)
-6dB FS
T
A
= +25°C
20
20
10
0
0 10 20 30 40 50 60 70 80 90 100
f
OUT
(MHz)
0
0
10 20 30 40 50 60 70 80 90 100
f
OUT
(MHz)
_______________________________________________________________________________________
5
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