PSoC
®
4: PSoC 4100S Datasheet
Programmable System-on-Chip (PSoC)
General Description
PSoC
®
4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with an
ARM
®
Cortex™-M0+ CPU. It combines programmable and reconfigurable analog and digital blocks with flexible automatic routing.
The PSoC 4100S product family is a member of the PSoC 4 platform architecture. It is a combination of a microcontroller with standard
communication and timing peripherals, a capacitive touch-sensing system (CapSense) with best-in-class performance, programmable
general-purpose continuous-time and switched-capacitor analog blocks, and programmable connectivity. PSoC 4100S products will
be upward compatible with members of the PSoC 4 platform for new applications and design needs.
Features
32-bit MCU Subsystem
■
■
■
Serial Communication
■
48-MHz ARM Cortex-M0+ CPU
Up to 64 KB of flash with Read Accelerator
Up to 8 KB of SRAM
Three independent run-time reconfigurable Serial
Communication Blocks (SCBs) with re-configurable I
2
C, SPI,
or UART functionality
Programmable Analog
■
Timing and Pulse-Width Modulation
■
■
■
■
Two opamps with reconfigurable high-drive external and
high-bandwidth internal drive and Comparator modes and ADC
input buffering capability. Opamps can operate in Deep Sleep
low-power mode.
12-bit 1-Msps SAR ADC with differential and single-ended
modes, and Channel Sequencer with signal averaging
Single-slope 10-bit ADC function provided by a capacitance
sensing block
Two current DACs (IDACs) for general-purpose or capacitive
sensing applications on any pin
Two low-power comparators that operate in Deep Sleep
low-power mode
Five 16-bit timer/counter/pulse-width modulator (TCPWM)
blocks
Center-aligned, Edge, and Pseudo-random modes
Comparator-based triggering of Kill signals for motor drive and
other high-reliability digital logic applications
Quadrature decoder
■
■
■
■
Up to 36 Programmable GPIO Pins
■
■
■
48-pin TQFP, 44-pin TQFP, 40-pin QFN, 32-pin QFN, and
35-ball WLCSP packages
Any GPIO pin can be CapSense, analog, or digital
Drive modes, strengths, and slew rates are programmable
Programmable Digital
■
Programmable logic blocks allowing Boolean operations to be
performed on port inputs and outputs
Deep Sleep mode with operational analog and 2.5-
A digital
system current
Clock Sources
■
■
■
32-kHz Watch Crystal Oscillator (WCO)
±2% Internal Main Oscillator (IMO)
32-kHz Internal Low-power Oscillator (ILO)
Low-Power 1.71-V to 5.5-V Operation
■
Capacitive Sensing
■
■
■
PSoC Creator Design Environment
■
Cypress CapSense Sigma-Delta (CSD) provides best-in-class
signal-to-noise ratio (SNR) (>5:1) and water tolerance
Cypress-supplied software component makes capacitive
sensing design easy
Automatic hardware tuning (SmartSense™)
Integrated Development Environment (IDE) provides
schematic design entry and build (with analog and digital
automatic routing)
Applications Programming Interface (API) component for all
fixed-function and programmable peripherals
■
Industry-Standard Tool Compatibility
■
LCD Drive Capability
■
LCD segment drive capability on GPIOs
After schematic entry, development can be done with
ARM-based industry-standard development tools
Cypress Semiconductor Corporation
Document Number: 002-00122 Rev. *K
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised April 3, 2018
PSoC
®
4: PSoC 4100S Datasheet
Development Support
Cypress provides a wealth of data at
www.cypress.com
to help you to select the right PSoC device for your design, and to help you
to quickly and effectively integrate the device into your design. For a comprehensive list of resources, see the knowledge base article
KBA86521, How to Design with PSoC 3, PSoC 4, and PSoC 5LP.
Following is an abbreviated list for PSoC 4:
■
■
■
Overview:
PSoC Portfolio, PSoC Roadmap
Product Selectors:
PSoC 1, PSoC 3, PSoC 4, PSoC 5LP
In addition, PSoC Creator includes a device selection tool.
Application notes: Cypress offers a large number of PSoC
application notes covering a broad range of topics, from basic
to advanced level. Recommended application notes for getting
started with PSoC 4 are:
❐
AN79953:
Getting Started With PSoC 4
❐
AN88619:
PSoC 4 Hardware Design Considerations
❐
AN86439:
Using PSoC 4 GPIO Pins
❐
AN57821:
Mixed Signal Circuit Board Layout
❐
AN81623:
Digital Design Best Practices
❐
AN73854:
Introduction To Bootloaders
❐
AN89610:
ARM Cortex Code Optimization
®
❐
AN85951:
PSoC 4 and PSoC Analog Coprocessor
®
Design Guide
CapSense
Technical Reference Manual (TRM) is in two documents:
❐
Architecture TRM
details each PSoC 4 functional block.
❐
Registers TRM
describes each of the PSoC 4 registers.
■
Software User Guide:
❐
A step-by-step guide for using PSoC Creator. The software
user guide shows you how the PSoC Creator build process
works in detail, how to use source control with PSoC Creator,
and much more.
Component Datasheets:
❐
The flexibility of PSoC allows the creation of new peripherals
(components) long after the device has gone into production.
Component datasheets provide all the information needed to
select and use a particular component, including a functional
description, API documentation, example code, and AC/DC
specifications.
Online:
■
■
In addition to print documentation, the
Cypress PSoC forums
connect you with fellow PSoC users and experts in PSoC from
around the world, 24 hours a day, 7 days a week.
■
Development Kits:
❐
CY8CKIT-041-41XX
PSoC 4100S CapSense Pioneer Kit, is
an easy-to-use and inexpensive development platform. This
kit includes connectors for Arduino™ compatible shields.
The
MiniProg3
device provides an interface for flash
programming and debug.
■
Document Number: 002-00122 Rev. *K
Page 2 of 41
PSoC
®
4: PSoC 4100S Datasheet
PSoC Creator
PSoC Creator
is a free Windows-based Integrated Design Environment (IDE). It enables concurrent hardware and firmware design
of PSoC 3, PSoC 4, and PSoC 5LP based systems. Create designs using classic, familiar schematic capture supported by over 100
pre-verified, production-ready PSoC Components; see the
list of component datasheets.
With PSoC Creator, you can:
1. Drag and drop component icons to build your hardware
system design in the main design workspace
2. Codesign your application firmware with the PSoC hardware,
using the PSoC Creator IDE C compiler
3. Configure components using the configuration tools
4. Explore the library of 100+ components
5. Review component datasheets
Figure 1. Multiple-Sensor Example Project in PSoC Creator
1
2
3
5
4
Document Number: 002-00122 Rev. *K
Page 3 of 41
PSoC
®
4: PSoC 4100S Datasheet
Contents
Functional Definition ........................................................ 6
CPU and Memory Subsystem ..................................... 6
System Resources ...................................................... 6
Analog Blocks .............................................................. 7
Programmable Digital Blocks ...................................... 7
Fixed Function Digital .................................................. 7
GPIO ........................................................................... 8
Special Function Peripherals ....................................... 8
Pinouts .............................................................................. 9
Alternate Pin Functions ............................................. 11
Power ............................................................................... 13
Mode 1: 1.8 V to 5.5 V External Supply .................... 13
Mode 2: 1.8 V ±5% External Supply .......................... 13
Electrical Specifications ................................................ 14
Absolute Maximum Ratings ...................................... 14
Device Level Specifications ....................................... 14
Analog Peripherals .................................................... 18
Digital Peripherals ..................................................... 25
Memory ..................................................................... 27
System Resources .................................................... 27
Ordering Information ...................................................... 30
Packaging ........................................................................ 32
Package Diagrams .................................................... 33
Acronyms ........................................................................ 37
Document Conventions ................................................. 39
Units of Measure ....................................................... 39
Revision History ............................................................. 40
Sales, Solutions, and Legal Information ...................... 41
Worldwide Sales and Design Support ....................... 41
Products .................................................................... 41
PSoC® Solutions ...................................................... 41
Cypress Developer Community ................................. 41
Technical Support ..................................................... 41
Document Number: 002-00122 Rev. *K
Page 4 of 41
PSoC
®
4: PSoC 4100S Datasheet
Figure 2. Block Diagram
PSoC 4100S
Architecture
32-bit
AHB- Lite
CPU Subsystem
SWD/TC
SPCIF
Cortex
M0+
48 MHz
FAST MUL
NVIC, IRQMUX
FLASH
64 KB
Read Accelerator
SRAM
4 KB
SRAM Controller
ROM
8 KB
ROM Controller
System Resources
Lite
Power
Sleep Control
WIC
POR
REF
PWRSYS
Clock
Clock Control
WDT
ILO
IMO
Reset
Reset Control
XRES
Test
TestMode Entry
Digital DFT
Analog DFT
System Interconnect (Single Layer AHB)
Peripherals
PCLK
Peripheral Interconnect (MMIO)
Programmable
Analog
2x SCB
-I2C/SPI/UART
IOSS GPIO
(5x ports)
x1
SARMUX
CTBm
2x Opamp x1
High Speed I/O Matrix& 2 x Programmable I/O
Power Modes
Active/ Sleep
DeepSleep
36x GPIOs, LCD
I/O Subsystem
PSoC 4100S devices include extensive support for
programming, testing, debugging, and tracing both hardware
and firmware.
The ARM Serial-Wire Debug (SWD) interface supports all
programming and debug features of the device.
Complete debug-on-chip functionality enables full-device
debugging in the final system using the standard production
device. It does not require special interfaces, debugging pods,
simulators, or emulators. Only the standard programming
connections are required to fully support debug.
The PSoC Creator IDE provides fully integrated programming
and debug support for the PSoC 4100S devices. The SWD
interface is fully compatible with industry-standard third-party
tools. The PSoC 4100S provides a level of security not possible
with multi-chip application solutions or with microcontrollers.
It has the following advantages:
■
■
■
The debug circuits are enabled by default and can be disabled
in firmware. If they are not enabled, the only way to re-enable
them is to erase the entire device, clear flash protection, and
reprogram the device with new firmware that enables debugging.
Thus firmware control of debugging cannot be over-ridden
without erasing the firmware thus providing security.
Additionally, all device interfaces can be permanently disabled
(device security) for applications concerned about phishing
attacks due to a maliciously reprogrammed device or attempts to
defeat security by starting and interrupting flash programming
sequences. All programming, debug, and test interfaces are
disabled when maximum device security is enabled. Therefore,
PSoC 4100S, with device security enabled, may not be returned
for failure analysis. This is a trade-off the PSoC 4100S allows the
customer to make.
Allows disabling of debug features
Robust flash protection
Allows customer-proprietary functionality to be implemented in
on-chip programmable blocks
Document Number: 002-00122 Rev. *K
WCO
SAR ADC
(12-bit)
2x LP Comparator
5x TCPWM
CapSense
Page 5 of 41
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