CY7C024AV
CY7C025AV
CY7C026AV
3.3 V, 4K/8K/16K × 16 Dual-Port
Static RAM
3.3 V, 4K/8K/16K × 16 Dual-Port Static RAM
Features
■
■
■
■
■
■
■
■
■
■
INT flag for port-to-port communication
Separate upper byte and lower byte control
Pin select for Master or Slave (M/S)
Commercial and industrial temperature ranges
Available in 100-pin Pb-free TQFP and 100-pin TQFP
True dual-ported memory cells which enable simultaneous
access of the same memory location
4, 8 or 16K × 16 organization
(CY7C024AV/025AV/026AV)
0.35 micron CMOS for optimum speed and power
High speed access: 20 ns and 25 ns
Low operating power
❐
Active: I
CC
= 115 mA (typical)
❐
Standby: I
SB3
= 10
A
(typical)
Fully asynchronous operation
Automatic power down
Expandable data bus to 32 bits or more using Master and Slave
chip select when using more than one device
On chip arbitration logic
Semaphores included to permit software handshaking
between ports
Functional Description
The CY7C024AV/025AV/026AV consist of an array of 4K, 8K, and
16K words of 16 bits each of dual-port RAM cells, IO and address
lines, and control signals (CE, OE, R/W). These control pins permit
independent access for reads or writes to any location in memory.
To handle simultaneous writes and reads to the same location, a
BUSY pin is provided on each port. Two Interrupt (INT) pins can be
used for port to port communication. Two Semaphore (SEM) control
pins are used for allocating shared resources. With the M/S pin, the
devices can function as a master (BUSY pins are outputs) or as a
slave (BUSY pins are inputs). They also have an automatic power
down feature controlled by CE. Each port has its own output enable
control (OE), which enables data to be read from the device.
For a complete list of related resources,
click here.
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■
■
■
■
Selection Guide
Parameter
Maximum Access Time
Typical Operating Current
Typical Standby Current for I
SB1
(Both ports TTL Level)
Typical Standby Current for I
SB3
(Both ports CMOS Level)
CY7C024AV/025AV/026AV
-20
20
120
35
10
CY7C024AV/025AV/026AV
-25
25
115
30
10
Unit
ns
mA
mA
A
Cypress Semiconductor Corporation
Document Number: 38-06052 Rev. *T
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised August 1, 2017
CY7C024AV
CY7C025AV
CY7C026AV
Logic Block Diagram
R/W
L
UB
L
R/W
R
UB
R
CE
L
LB
L
OE
L
8
8
8
CE
R
LB
R
OE
R
[1]
IO
8L
–IO
15L
[1]
[2]
IO
0L
–IO
7L
IO
Control
IO
Control
8
IO
8L
– IO
15R
IO
0L
– IO
7R
[2]
A
0L
–A
11/1213L
[3]
[3]
12/13/14
Address
Decode
12/13/14
True Dual-Ported
RAM Array
Address
Decode
12/13/14
12/13/14
A
0R
–A
11/12/13R
[3]
[3]
A
0L
–A
11/12/13L
CE
L
OE
L
R/W
L
SEM
L
[4]
BUSY
L
INT
L
UB
L
LB
L
Interrupt
Semaphore
Arbitration
A
0R
–A
11/12/13R
CE
R
OE
R
R/W
R
SEM
R
[4]
M/S
BUSY
R
INT
R
UB
R
LB
R
Notes
1. IO
8
–IO
15
for × 16 devices
2. IO
0
–IO
7
for × 16 devices
3. A
0
–A
11
for 4K devices; A
0
–A
12
for 8K devices; A
0
–A
13
for 16K devices.
4. BUSY is an output in master mode and an input in slave mode.
Document Number: 38-06052 Rev. *T
Page 2 of 24
CY7C024AV
CY7C025AV
CY7C026AV
Contents
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 5
Functional Overview ........................................................ 6
Write Operation ........................................................... 6
Read Operation ........................................................... 7
Interrupts ..................................................................... 7
Busy ............................................................................ 7
Master/Slave ............................................................... 7
Semaphore Operation ................................................. 8
Maximum Ratings ............................................................. 9
Operating Range ............................................................... 9
Electrical Characteristics ................................................. 9
Capacitance .................................................................... 10
AC Test Loads and Waveforms ..................................... 10
Data Retention Mode ...................................................... 10
Timing .............................................................................. 10
Switching Characteristics .............................................. 11
Switching Waveforms .................................................... 13
Ordering Information ...................................................... 19
4K × 16 3.3 V Asynchronous Dual-Port SRAM ......... 19
8K × 16 3.3 V Asynchronous Dual-Port SRAM ......... 19
16K × 16 3.3 V Asynchronous Dual-Port SRAM ....... 19
Ordering Code Definitions ......................................... 19
Package Diagram ............................................................ 20
Acronyms ........................................................................ 21
Document Conventions ................................................. 21
Units of Measure ....................................................... 21
Document History Page ................................................. 22
Sales, Solutions, and Legal Information ...................... 24
Worldwide Sales and Design Support ....................... 24
Products .................................................................... 24
PSoC® Solutions ...................................................... 24
Cypress Developer Community ................................. 24
Technical Support ..................................................... 24
Document Number: 38-06052 Rev. *T
Page 3 of 24
CY7C024AV
CY7C025AV
CY7C026AV
Pin Configurations
Figure 1. 100-pin TQFP pinout (Top View)
OE
L
V
CC
R/W
L
SEM
L
CE
L
UB
L
LB
L
NC
[5]
A
11L
A
10L
IO
4L
IO
3L
IO
2L
GND
IO
9L
IO
8L
IO
7L
IO
6L
IO
5L
IO
1L
IO
0L
A
9L
A
8L
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
NC
NC
NC
NC
IO
10L
IO
11L
IO
12L
IO
13L
GND
IO
14L
IO
15L
V
CC
GND
IO
0R
IO
1R
IO
2R
V
CC
IO
3R
IO
4R
IO
5R
IO
6R
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
NC
NC
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
BUSY
L
GND
M/S
BUSY
R
INT
R
A
0R
A
1R
A
2R
A
3R
A
4R
NC
NC
NC
NC
CY7C024AV (4K × 16)
CY7C025AV (8K × 16)
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
IO
7R
IO
8R
IO
9R
IO
10R
IO
11R
IO
12R
IO
13R
IO
14R
GND
IO
15R
Œ
R
R\W
R
GND
SEM
R
CE
R
UB
R
LB
R
NC
[6]
A
11R
A
10R
A
9R
A
8R
Notes
5. A
12L
on the CY7C025AV.
6. A
12R
on the CY7C025AV.
Document Number: 38-06052 Rev. *T
A
7R
A
6R
A
5R
A
7L
A
6L
Page 4 of 24
CY7C024AV
CY7C025AV
CY7C026AV
Pin Configurations
(continued)
IO
IO
IO
IO
IO
IO
G
IO
IO1L
O
IO0L
R
OE
L
G
VCC
SE
R/
WL
C
SEM
L
U
CE
L
UB
L
N
LB
L
A
A13L
A
A12L
A11L
A10L
A9L
A8L
A7L
Figure 2. 100-pin TQFP pinout (Top View)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
NC
NC
NC
NC
IO10L
IO11L
IO12L
IO13L
GND
IO14L
IO15L
VCC
GND
IO0R
IO1R
IO2R
VCC
IO3R
IO4R
IO5R
IO6R
NC
NC
NC
NC
75
1
2
74
3
73
72
4
71
5
70
6
69
7
68
8
67
9
66
10
65
11
64
12
63
13
14
62
61
15
60
16
59
17
18
58
19
57
20
56
21
55
22
54
23
53
24
52
25
51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
NC
NC
A6L
A5L
A4L
A3L
A2L
A1L
A0L
INT
L
BUSY
L
GND
M/
S
BUSY
R
INT
R
A0R
A1R
A2R
A3R
A4R
A5R
NC
NC
NC
IO9L
IO8L
IO7L
IO6L
IO5L
IO4L
IO3L
IO2L
GND
IO
IO
CY7C026AV (16K × 16)
IO15R
OE
R
R/
WR
GND
SEM
R
CE
R
IO7R
IO8R
IO9R
IO10R
IO11R
IO12R
IO13R
IO14R
GND
UB
R
LB
R
A13R
A12R
A11R
A10R
Pin Definitions
Left Port
CE
L
R/W
L
OE
L
A
0L
–A
13L
IO
0L
–IO
15L
SEM
L
UB
L
LB
L
INT
L
BUSY
L
M/S
V
CC
GND
NC
CE
R
R/W
R
OE
R
A
0R
–A
13R
IO
0R
–IO
15R
SEM
R
UB
R
LB
R
INT
R
BUSY
R
Right Port
Chip Enable
Read and Write Enable
Output Enable
Address (A
0
–A
11
for 4K devices; A
0
–A
12
for 8K devices; A
0
–A
13
for 16K)
Data Bus Input and Output
Semaphore Enable
Upper Byte Select (IO
8
–IO
15
for × 16 devices)
Lower Byte Select (IO
0
–IO
7
for × 16 devices)
Interrupt Flag
Busy Flag
Master or Slave Select
Power
Ground
No Connect
Description
Document Number: 38-06052 Rev. *T
A9R
A8R
A7R
A6R
Page 5 of 24
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