19-1687; Rev 2; 12/10
KIT
ATION
EVALU
BLE
AVAILA
400ksps/300ksps, Single-Supply, Low-Power,
Serial 12-Bit ADCs with Internal Reference
General Description
The MAX1284/MAX1285 12-bit analog-to-digital con-
verters (ADCs) combine a high-bandwidth track/hold
(T/H), a serial interface with high conversion speed, an
internal +2.5V reference, and low power consumption.
The MAX1284 operates from a single +4.5V to +5.5V
supply. The MAX1285 operates from a single +2.7V to
+3.6V supply.
The 3-wire serial interface connects directly to
SPI™/QSPI™/ MICROWIRE™ devices without external
logic. The devices use an external serial-interface clock
to perform successive-approximation analog-to-digital
conversions.
Low power, ease of use, and small package size make
these converters ideal for remote-sensor and data-acqui-
sition applications or for other circuits with demanding
power consumption and space requirements. The
MAX1284/MAX1285 are available in 8-pin SO packages.
These devices are pin-compatible, higher-speed ver-
sions of the MAX1240/MAX1241. Refer to the respec-
tive data sheets for more information.
____________________________Features
o
Single-Supply Operation
+4.5V to +5.5V (MAX1284)
+2.7V to +3.6V (MAX1285)
o
±1LSB (max) DNL, ±1LSB (max) INL
o
400ksps Sampling Rate (MAX1284)
o
Internal Track/Hold
o
+2.5V Internal Reference
o
Low Power: 2.5mA (400ksps)
o
SPI/QSPI/MICROWIRE 3-Wire Serial-Interface
o
Pin-Compatible, High-Speed Upgrades to
MAX1240/MAX1241
o
8-Pin SO Package
MAX1284/MAX1285
Ordering Information
PART
MAX1284BCSA+
MAX1284BESA+
MAX1285BCSA+
MAX1285BESA+
TEMP RANGE
0°C to +70°C
0°C to +70°C
PIN-
SUPPLY
PACKAGE VOLTAGE (V)
8 SO
8 SO
5
5
2.7 to 3.6
2.7 to 3.6
Applications
Portable Data Logging
Data Acquisition
Medical Instruments
Battery-Powered Instruments
Pen Digitizers
Process Control
-40°C to +85°C 8 SO
-40°C to +85°C 8 SO
+Denotes
a lead(Pb)-free/RoHS-compliant package.
Pin Configuration
TOP VIEW
+
V
DD
AIN
1
2
8
7
SCLK
CS
DOUT
GND
SHDN
3
CONTROL
LOGIC
CS
SCLK
7
8
Functional Diagram
V
DD
1
SHDN 3
REF 4
MAX1284
MAX1285
6
5
INT
CLOCK
OUTPUT
SHIFT
REGISTER
6
DOUT
SO
AIN
2
T/H
12-BIT
SAR
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
REF
+2.5V REFERENCE
4
5
GND
MAX1284
MAX1285
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
400ksps/300ksps, Single-Supply, Low-Power,
Serial 12-Bit ADCs with Internal Reference
MAX1284/MAX1285
ABSOLUTE MAXIMUM RATINGS
V
DD
to GND .............................................................-0.3V to +6V
AIN to GND................................................-0.3V to (V
DD
+ 0.3V)
REF to GND ...............................................-0.3V to (V
DD
+ 0.3V)
Digital Inputs to GND...............................................-0.3V to +6V
DOUT to GND............................................-0.3V to (V
DD
+ 0.3V)
DOUT Current ..................................................................±25mA
Continuous Power Dissipation (T
A
= +70°C)
8-Pin SO (derate 5.88mW/°C above +70°C) ..............471mW
Operating Temperature Ranges
MAX1284BCSA/MAX1285BCSA .......................0°C to +70°C
MAX1284BESA/MAX1285BESA .....................-40°C to +85°C
Storage Temperature Range............................-60°C to +150°C
Lead Temperature (soldering, 10s) ................................+300°C
Soldering Temperature (reflow) ......................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS—MAX1284
(V
DD
= +4.5V to +5.5V; f
SCLK
= 6.4MHz, 50% duty cycle, 16 clocks/conversion cycle (400ksps), 4.7µF capacitor at REF, T
A
= T
MIN
to
T
MAX,
unless otherwise noted. Typical values are at T
A
= +25°C.)
PARAMETER
DC ACCURACY
(Note 1)
Resolution
Relative Accuracy (Note 2)
Differential Nonlinearity
Offset Error
Gain Error (Note 3)
Gain-Error Temperature
Coefficient
DYNAMIC SPECIFICATIONS
(100kHz sine wave, 2.5V
P-P
, clock = 6.4MHz)
Signal-to-Noise Plus Distortion
Ratio
Total Harmonic Distortion
Spurious-Free Dynamic Range
Intermodulation Distortion
Full-Power Bandwidth
Full-Linear Bandwidth
CONVERSION RATE
Conversion Time (Note 4)
Track/Hold Acquisition Time
Aperture Delay
Aperture Jitter
Serial Clock Frequency
Duty Cycle
ANALOG INPUT (AIN)
Input Voltage Range
Input Capacitance
V
AIN
0
18
2.5
V
pF
t
SCLK
0.5
40
t
CONV
t
ACQ
10
< 50
6.4
60
2.5
468
µs
ns
ns
ps
MHz
%
SINAD
THD
SFDR
IMD
f
IN1
= 99Hz, f
IN2
= 102Hz
-3dB point
SINAD > 68dB
Up to the 5th harmonic
70
-80
80
76
6
350
dB
dB
dB
dB
MHz
kHz
±0.8
INL
DNL
No missing codes over temperature
12
±1.0
±1.0
±6.0
±6.0
Bits
LSB
LSB
LSB
LSB
ppm/°C
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
2
_______________________________________________________________________________________
400ksps/300ksps, Single-Supply, Low-Power,
Serial 12-Bit ADCs with Internal Reference
ELECTRICAL CHARACTERISTICS—MAX1284 (continued)
(V
DD
= +4.5V to +5.5V; f
SCLK
= 6.4MHz, 50% duty cycle, 16 clocks/conversion cycle (400ksps), 4.7µF capacitor at REF, T
A
= T
MIN
to
T
MAX,
unless otherwise noted. Typical values are at T
A
= +25°C.)
PARAMETER
INTERNAL REFERENCE
REF Output Voltage
REF Short-Circuit Current
REF Output Tempco
Load Regulation (Note 5)
Capacitive Bypass at REF
DIGITAL INPUTS (SCLK, CS, SHDN)
Input High Voltage
Input Low Voltage
Input Hysteresis
Input Leakage
Input Capacitance
DIGITAL OUTPUT (DOUT)
Output Voltage Low
Output Voltage High
Three-State Leakage Current
Three-State Output Capacitance
POWER SUPPLY
Positive Supply Voltage (Note 6)
Positive Supply Current (Note 7)
Shutdown Supply Current
Power-Supply Rejection
VDD
IDD
I
SHDN
PSR
V
DD
= +5.5V
SCLK = V
DD
,
SHDN
= GND
V
DD
= +5V ±10%, midscale input
4.5
2.5
2
±0.5
5.5
4.0
10
±2.0
V
mA
µA
mV
V
INH
V
INL
V
HYST
I
IN
C
IN
V
OL
V
OH
I
L
C
OUT
I
SINK
= 5mA
I
SOURCE
= 1mA
V
CS
= +5V
V
CS
= +5V
15
4
±10
V
IN
= 0V or V
DD
15
0.4
0.2
±1
3.0
0.8
V
V
V
µA
pF
V
V
µA
pF
TC V
REF
0 to 1mA output load
4.7
V
REF
T
A
= +25°C
2.48
2.50
30
±15
0.1
2.0
10
2.52
V
mA
ppm/°C
mV/mA
µF
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MAX1284/MAX1285
ELECTRICAL CHARACTERISTICS—MAX1285
(V
DD
= +2.7V to +3.6V; f
SCLK
= 4.8MHz, 50% duty cycle, 16 clocks/conversion cycle (300ksps), 4.7µF capacitor at REF, T
A
= T
MIN
to
T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.)
PARAMETER
DC ACCURACY
(Note 1)
Resolution
Relative Accuracy (Note 2)
Differential Nonlinearity
Offset Error
Gain Error (Note 3)
Gain-Error Temperature
Coefficient
±1.6
INL
DNL
No missing codes over temperature
12
±1.0
±1.0
±6.0
±6.0
Bits
LSB
LSB
LSB
LSB
ppm/°C
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
_______________________________________________________________________________________
3
400ksps/300ksps, Single-Supply, Low-Power,
Serial 12-Bit ADCs with Internal Reference
MAX1284/MAX1285
ELECTRICAL CHARACTERISTICS—MAX1285 (continued)
(V
DD
= +2.7V to +3.6V; f
SCLK
= 4.8MHz, 50% duty cycle, 16 clocks/conversion cycle (300ksps), 4.7µF capacitor at REF, T
A
= T
MIN
to
T
MAX,
unless otherwise noted. Typical values are at T
A
= +25°C.)
PARAMETER
Signal-to-Noise Plus Distortion
Ratio
Total Harmonic Distortion
Spurious-Free Dynamic Range
Intermodulation Distortion
Full-Power Bandwidth
Full-Linear Bandwidth
CONVERSION RATE
Conversion Time (Note 4)
Track/Hold Acquisition Time
Aperture Delay
Aperture Jitter
Serial Clock Frequency
Duty Cycle
ANALOG INPUT (AIN)
Input Voltage Range
Input Capacitance
INTERNAL REFERENCE
REF Output Voltage
REF Short-Circuit Current
REF Output Tempco
Load Regulation (Note 5)
Capacitive Bypass at REF
DIGITAL INPUTS (SCLK, CS, SHDN)
Input High Voltage
V
INH
Input Low Voltage
Input Hysteresis
Input Leakage
Input Capacitance
DIGITAL OUTPUT (DOUT)
Output Voltage Low
Output Voltage High
Three-State Leakage Current
Three-State Output Capacitance
POWER SUPPLY
Positive Supply Voltage (Note 6)
Positive Supply Current (Note 7)
Shutdown Supply Current
Power-Supply Rejection
VDD
IDD
I
SHDN
PSR
2.7
V
DD
= +3.6V
SCLK = V
DD
,
SHDN
= GND
V
DD
= +2.7V to 3.6V, midscale input
2.5
2
±0.5
3.6
3.5
10
±2.0
V
mA
µA
mV
V
INL
V
HYST
I
IN
C
IN
V
OL
V
OH
I
L
C
OUT
V
IN
= 0V or V
DD
15
I
SINK
= 5mA
I
SOURCE
= 0.5mA
V
CS
= +3V
V
CS
= +3V
V
DD
- 0.5
±10
15
0.4
0.2
±1
V
REF
T
A
= +25°C
TC V
REF
0 to 0.75mA output load
4.7
2.0
0.8
2.48
2.50
15
±15
0.1
2.0
10
2.52
V
mA
ppm/°C
mV/mA
µF
V
V
V
µA
pF
V
V
µA
pF
V
AIN
0
18
2.5
V
pF
t
SCLK
0.5
40
t
CONV
t
ACQ
10
< 50
4.8
60
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DYNAMIC SPECIFICATIONS
(75kHz sine wave, 2.5V
P-P
, f
SAMPLE
= 300ksps, f
SCLK
= 4.8MHz)
SINAD
THD
SFDR
IMD
Up to the 5th harmonic
f
IN1
= 73kHz, f
IN2
= 77kHz
-3dB point
SINAD > 68dB
3.3
625
70
-80
80
76
3
250
dB
dB
dB
dB
MHz
kHz
µs
ns
ns
ps
MHz
%
4
_______________________________________________________________________________________
400ksps/300ksps, Single-Supply, Low-Power,
Serial 12-Bit ADCs with Internal Reference
TIMING CHARACTERISTICS—MAX1284 (Figures 1, 2, 8, 9)
(V
DD
= +4.5V to +5.5V, T
A
= T
MIN
to T
MAX,
unless otherwise noted.)
PARAMETER
SCLK Period
SCLK Pulse-Width High
SCLK Pulse-Width Low
CS
Fall to SCLK Rise Setup
SCLK Rise to
CS
Rise Hold
SCLK Rise to
CS
Fall Ignore
CS
Rise to SCLK Rise Ignore
SCLK Rise to DOUT Hold
SCLK Rise to DOUT Valid
CS
Rise to DOUT Disable
CS
Fall to DOUT Enable
CS
Pulse-Width High
SYMBOL
t
CP
t
CH
t
CL
t
CSS
t
CSH
t
CSO
t
CS1
t
DOH
t
DOV
t
DOD
t
DOE
t
CSW
C
LOAD
= 20pF
C
LOAD
= 20pF
C
LOAD
= 20pF
C
LOAD
= 20pF
100
10
CONDITIONS
MIN
156
62
62
35
0
35
35
10
80
65
65
TYP
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MAX1284/MAX1285
TIMING CHARACTERISTICS—MAX1285 (Figures 1, 2, 8, 9)
(V
DD
= +2.7V to +3.6V, T
A
= T
MIN
to T
MAX,
unless otherwise noted.)
PARAMETER
SCLK Period
SCLK Pulse-Width High
SCLK Pulse-Width Low
CS
Fall to SCLK Rise Setup
SCLK Rise to
CS
Rise Hold
SCLK Rise to
CS
Fall Ignore
CS
Rise to SCLK Rise Ignore
SCLK Rise to DOUT Hold
SCLK Rise to DOUT Valid
CS
Rise to DOUT Disable
CS
Fall to DOUT Enable
CS
Pulse-Width High
SYMBOL
t
CP
t
CH
t
CL
t
CSS
t
CSH
t
CSO
t
CS1
t
DOH
t
DOV
t
DOD
t
DOE
t
CSW
C
LOAD
= 20pF
C
LOAD
= 20pF
C
LOAD
= 20pF
C
LOAD
= 20pF
100
13
CONDITIONS
MIN
208
83
83
45
0
45
45
13
100
85
85
TYP
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 1:
Tested at V
DD
= V
DD(MIN)
.
Note 2:
Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3:
Internal reference, offset, and reference errors nulled.
Note 4:
Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 5:
External load should not change during conversion for specified accuracy. Guaranteed specification limit of 2mV/mA due to
production test limitations.
Note 6:
Electrical characteristics are guaranteed from V
DD(MIN)
to V
DD(MAX)
. For operations beyond this range, see
Typical
Operating Characteristics.
Note 7:
MAX1284 tested with 20pF on D
OUT
and f
SCLK
= 6.4MHz, 0 to 5V. MAX1285 tested with same loads, f
SCLK
= 4.8MHz,
0 to 3V. D
OUT
= full scale.
_______________________________________________________________________________________
5
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