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HCC4724B: 产品描述8 BIT ADDRESSABLE LATCH; 文件大小286KB，共14页; 制造商ST(意法半导体); 官网地址http://www.st.com/

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HCC4724B概述

8 BIT ADDRESSABLE LATCH

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HCC4724B

HCF4724B

8 BIT ADDRESSABLE LATCH

SERIAL DATA INPUT - ACTIVE PARALLEL

OUTPUT

STORAGE REGISTER CAPABILITY - MASTER

CLEAR

CAN FUNCTION AS DEMULTIPLEXER

STANDARDIZED, SYMMETRICAL OUTPUT

CHARACTER

100% TESTED FOR QUIESCENT CURRENT

AT 20V

MAXIMUM INPUT CURRENT OF 1µA AT 18V

(full package-temperature range), 100nA AT 18V

AND 25

NOISE MARGIN (full package-temperature

range) = 1V AT V

= 5V, 2V AT V

= 10V, 2.5V

AT V

= 15V

5V, 10V, AND 15V PARAMETRIC RATINGS

MEETS ALL REQUIREMENTS OF JEDEC TEN-

TATIVE STANDARD N. 13A, ” STANDARD

SPECIFICATIONS FOR DESCRIPTION OF ’ B

’ SERIES CMOS DEVICES ”

(Plastic Package)

(Ceramic Package)

(Micro Package)

(Chip Carrier)

ORDER CODES :

HCC4724BF

HCF4724BM1

HCF4724BEY

HCF4724BC1

APPLICATION

MULTI-LINE DECODERS

A/D CONVERTERS

PIN CONNECTIONS

DESCRIPTION

The

HCC/HCF4724B

8-bit addressable latch is a

serial-input, parallel-output storage register that can

perform a variety of functions.

Data are inputted to a particular bit in the latch when

that bit is addressed (by means of inputs A0, A1, A2)

and when WRITE DISABLE is at low level. When

WRITE DISABLE is high, data entry is inhibited

however, all 8 outputs can be continuously read in-

dependent of WRITE DISABLE and address inputs.

A master RESET input is available, which resets all

bits to a logic ” 0 ” level when RESET and WRITE

DISABLE are at a high level. When RESET is at a

high level, and WRITE DISABLE is at a low level, the

latch acts as a 1-of-8 demultiplexer ; the bit that is

addressed has an active output which follows the

data input, while all unaddressed bits are held to a

logic ” 0 ” level.

September 1988

1/14

HCC4724B相似产品对比

	HCC4724B	HCC4724BF	HCF4724BC1	HCF4724B	HCF4724BM1	HCF4724BEY
描述	8 BIT ADDRESSABLE LATCH	8 BIT ADDRESSABLE LATCH	8 BIT ADDRESSABLE LATCH	8 BIT ADDRESSABLE LATCH	8 BIT ADDRESSABLE LATCH	8 BIT ADDRESSABLE LATCH
是否Rohs认证	-	不符合	符合	-	符合	符合
厂商名称	-	ST(意法半导体)	ST(意法半导体)	-	ST(意法半导体)	ST(意法半导体)
零件包装代码	-	DIP	QLCC	-	SOIC	DIP
包装说明	-	DIP, DIP16,.3	PLASTIC, LCC-20	-	SOP-16	PLASTIC, DIP-16
针数	-	16	20	-	16	16
Reach Compliance Code	-	_compli	compli	-	compli	compliant
其他特性	-	1:8 DMUX FOLLOWED BY LATCH; RESET ACTIVE ONLY WHEN LATCH ENABLE IS HIGH	1:8 DMUX FOLLOWED BY LATCH; RESET ACTIVE ONLY WHEN LATCH ENABLE IS HIGH	-	1:8 DMUX FOLLOWED BY LATCH	1:8 DMUX FOLLOWED BY LATCH
系列	-	4000/14000/40000	4000/14000/40000	-	4000/14000/40000	4000/14000/40000
JESD-30 代码	-	R-GDIP-T16	S-PQCC-J20	-	R-PDSO-G16	R-PDIP-T16
JESD-609代码	-	e0	e3	-	e4	e3
负载电容（CL）	-	50 pF	50 pF	-	50 pF	50 pF
逻辑集成电路类型	-	D LATCH	D LATCH	-	D LATCH	D LATCH
位数	-	1	1	-	1	1
功能数量	-	1	1	-	1	1
端子数量	-	16	20	-	16	16
最高工作温度	-	125 °C	85 °C	-	125 °C	125 °C
最低工作温度	-	-55 °C	-40 °C	-	-55 °C	-55 °C
输出极性	-	TRUE	TRUE	-	TRUE	TRUE
封装主体材料	-	CERAMIC, GLASS-SEALED	PLASTIC/EPOXY	-	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	-	DIP	QCCJ	-	SOP	DIP
封装等效代码	-	DIP16,.3	LDCC20,.4SQ	-	SOP16,.25	DIP16,.3
封装形状	-	RECTANGULAR	SQUARE	-	RECTANGULAR	RECTANGULAR
封装形式	-	IN-LINE	CHIP CARRIER	-	SMALL OUTLINE	IN-LINE
峰值回流温度（摄氏度）	-	NOT SPECIFIED	NOT SPECIFIED	-	NOT SPECIFIED	NOT SPECIFIED
电源	-	3/18 V	3/15 V	-	5/15 V	5/15 V
传播延迟（tpd）	-	400 ns	400 ns	-	400 ns	400 ns
认证状态	-	Not Qualified	Not Qualified	-	Not Qualified	Not Qualified
座面最大高度	-	5.08 mm	4.57 mm	-	1.75 mm	5.1 mm
最大供电电压 (Vsup)	-	18 V	15 V	-	20 V	20 V
最小供电电压 (Vsup)	-	3 V	3 V	-	3 V	3 V
标称供电电压 (Vsup)	-	5 V	5 V	-	5 V	5 V
表面贴装	-	NO	YES	-	YES	NO
技术	-	CMOS	CMOS	-	CMOS	CMOS
温度等级	-	MILITARY	INDUSTRIAL	-	MILITARY	MILITARY
端子面层	-	Tin/Lead (Sn/Pb)	Matte Tin (Sn)	-	Nickel/Palladium/Gold (Ni/Pd/Au)	Matte Tin (Sn)
端子形式	-	THROUGH-HOLE	J BEND	-	GULL WING	THROUGH-HOLE
端子节距	-	2.54 mm	1.27 mm	-	1.27 mm	2.54 mm
端子位置	-	DUAL	QUAD	-	DUAL	DUAL
处于峰值回流温度下的最长时间	-	NOT SPECIFIED	NOT SPECIFIED	-	NOT SPECIFIED	NOT SPECIFIED
触发器类型	-	LOW LEVEL	LOW LEVEL	-	LOW LEVEL	LOW LEVEL
宽度	-	7.62 mm	8.965 mm	-	3.9 mm	7.62 mm

HCC4724B

HCC4724B概述

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