HCC/HCF4014B
HCC/HCF4021B
8-STAGE STATIC SHIFT REGISTERS
4014B
4021B
SYNCHRONOUS PARALLEL OR
SERIAL INPUT/SERIAL OUTPUT
lines and synchronous with the positive transition of
the clock line. In the
HCC/HCF4021B,
the CLOCK
input of the internal stage is ”forced” whenasynchro-
nous parallel entry is made. Register expansion
using multiple package is permitted.
.
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.
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.
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ASYNCHRONOUS PARALLEL
INPUT OR SYNCHRONOUS
SERIAL INPUT/SERIAL OUTPUT
MEDIUM-SPEED OPERATION-12MHz (typ.)
CLOCK RATE AT V
DD
– V
SS
= 10V
FULLY STATIC OPERATION
8 MASTER-SLAVE FLIP-FLOPS PLUS OUT-
PUT BUFFERING AND CONTROL GATING
QUIESCENT CURRENT SPECIFIED TO 20V
FOR HCC DEVICE
5V, 10V AND 15V PARAMETRIC RATINGS
INPUT CURRENT OF 100nA AT 18V AND 25°C
FOR HCC DEVICE
100% TESTED FOR QUIESCENT CURRENT
MEETS ALL REQUIREMENTS OF JEDEC TEN-
TATIVE STANDARD N
o
13A, ”STANDARD
SPECIFICATIONS FOR DESCRIPTION OF ”B”
SERIES CMOS DEVICES”
EY
(Plastic Package)
F
(Ceramic Package)
M1
(Micro Package)
C1
(Plastic Chip Carrier)
DESCRIPTION
The
HCC4014B, HCC4021B
(extended temperatu-
re range) and the
HCF4014B, HCF4021B
(interme-
diate temperature range) are monolithic integrated
circuits, available in 16-lead dual in-line plastic or ce-
ramic package and plastic micro package. The
HCC/HCF4014B
and
HCC/HCF4021B
series types
are 8-stage parallel-or serial-input/serial-output re-
gisters having common CLOCK and PARAL-
LEL/SERIAL CONTROL inputs, a single SERIAL
data input, and individual parallel ”JAM” inputs to
each register stage. Each register stage is a D type,
master-slave flip-flop in addition to an output from
stage 8, ”Q” outputs are also available from stages
6 and 7. Parallel as well as serial entry is made into
the register synchronously with the positive clock li-
ne transition in the
HCC/HCF4014B.
In the
HCC/HCF4021B
serial entry is synchronous with
the clock but parallel entry is asynchronous. In both
types, entry is controlled by the PARALLEL/SERIAL
CONTROL input. When the PARALLEL/SERIAL
CONTROL input is low, data is serially shifted into
the 8-stage register synchronously with the positive
transition of the clock line. When the PARAL-
LEL/SERIAL CONTROL input is high, data is jam-
med into the 8-stage register via the parallel input
November 1996
ORDER CODES :
HCC40XXBF
HCF40XXBM1
HCF40XXBEY
HCF40XXBC1
PIN CONNECTIONS
1/13
HCC/HCF4014B/4021B
FUNCTIONAL DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symbol
V
DD
*
V
i
I
I
P
to t
Parameter
Supply Voltage :
HC C
Types
H CF
Types
Input Voltage
DC Input Current (any one input)
Total Power Dissipation (per package)
Dissipation per Output Transistor
for T
o p
= Full Package-temperature Range
Operating Temperature :
HCC
Types
H CF
Types
Storage Temperature
Value
– 0.5 to + 20
– 0.5 to + 18
– 0.5 to V
DD
+ 0.5
±
10
200
100
– 55 to + 125
– 40 to + 85
– 65 to + 150
Unit
V
V
V
mA
mW
mW
°C
°C
°C
T
op
T
stg
Stresses above those listed under ”Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for external periods may affect device reliability.
* All voltage values are referred to V
SS
pin voltage.
RECOMMENDED OPERATING CONDITIONS
Symbol
V
DD
V
I
T
op
Parameter
Supply Voltage :
HCC
Types
HC F
Types
Input Voltage
Operating Temperature :
HCC
Types
H CF
Types
Value
3 to 18
3 to 15
0 to V
DD
– 55 to + 125
– 40 to + 85
Unit
V
V
V
°C
°C
2/13
HCC/HCF4014B/4021B
STATIC ELECTRICAL CHARACTERISTICS
(continued)
Test Conditions
Symbol
Parameter
V
I
(V)
0/ 5
HCC 0/ 5
Types 0/10
0/15
0/ 5
0/ 5
HCF
Types 0/10
0/15
I
OL
Output
Sink
Current
0/ 5
HCC
0/10
Types
0/15
0/ 5
HCF
0/10
Types
0/15
I
IH
, I
IL
Input
Leakage
Current
HCC 0/18
Types
HCF
0/15
Types
Any Input
V
O
(V)
2.5
4.6
9.5
13.5
2.5
4.6
9.5
13.5
0.4
0.5
1.5
0.4
0.5
1.5
Value
Unit
|I
O
| V
D D
T
L o w
*
25
°C
T
Hi g h
*
(µA) (V)
Min. Max. Min. Typ. Max. Min. Max.
5
5
10
15
5
5
10
15
5
10
15
5
10
15
18
Any Input
15
– 2
– 0.64
– 1.6
– 4.2
– 1.53
– 0.52
– 1.3
– 3.6
0.64
1.6
4.2
0.52
1.3
3.6
±
0.1
±
0.3
– 1.6 – 3.2
– 0.51 – 1
– 1.3 – 2.6
– 3.4 – 6.8
– 1.36 – 3.2
– 0.44 – 1
– 1.1 – 2.6
– 3.0 – 6.8
0.51
1.3
3.4
0.44
1.1
3.0
1
2.6
6.8
1
2.6
6.8
±10
– 5
±
0.1
±10
– 5
±
0.3
5
7.5
– 1.15
– 0.36
– 0.9
– 2.4
– 1.1
– 0.36
– 0.9
– 2.4
0.36
0.9
2.4
0.36
0.9
2.4
±
1
±
1
µA
mA
mA
I
OH
Output
Drive
Current
C
I
Input Capacitance
pF
* T
Low
= – 55°C for
HCC
device : – 40°C for
HCF
device.
* T
High
= + 125°C for
HCC
device : + 85°C for
HCF
device.
The Noise Margin for both ”1” and ”0” level is : 1V min. with V
DD
= 5V, 2V min. with V
DD
= 10V, 2.5 V min. with V
DD
= 15V.
DYNAMIC ELECTRICAL CHARACTERISTICS
(T
amb
= 25°C, C
L
= 50pF, R
L
= 200kΩ,
typical temperature coefficient for all V
DD
= 0.3%/°C values, all input rise and fall time = 20ns)
Symbol
Parameter
Test Conditions
V
D D
(V)
Min.
5
10
15
t
THL
, t
T L H
Transition Time
5
10
15
f
CL
*
Maximum Clock Input Frequency
5
10
15
t
W
Clock Pulse Width
5
10
15
3
6
8.5
180
80
50
Value
Typ.
160
80
60
100
50
40
6
12
17
90
40
25
ns
MHz
Max.
320
160
120
200
100
80
ns
ns
Unit
CLOCKED OPERATION
t
P L H
, t
P HL
Propagation Delay Time
* If more than one unit is cascaded t
r
CL should be made less than or equal to the sum of the transition time and the fixed propaga
tion delay of
the output of the driving stage of the estimated capacitive load.
5/13
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