CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Typical Operating Conditions
These represent the conditions under which the part was developed and are suggested as guidelines.
PARAMETER
Case Temperature
V
CC
with Respect to AGND
V
EE
with Respect to AGND
V
BAT
with Respect to BGND
-40
o
C to 85
o
C
-40
o
C to 85
o
C
-40
o
C to 85
o
C
CONDITIONS
MIN
-40
4.75
-5.25
-58
TYP
-
-
-
-
MAX
100
5.25
-4.75
-24
UNITS
o
C
V
V
V
Electrical Specifications
T
A
= -40
o
C to 85
o
C, V
CC
= +5V
±5%,
V
EE
= -5V
±5%,
V
BAT
= -48V, AGND = BGND = 0V, R
DC1
= R
DC2
= 41.2kΩ,
R
D
= 39kΩ, R
SG
= 0Ω, R
F1
= R
F2
= 0Ω, C
HP
= 10nF, C
DC
= 1.5µF, Z
L
= 600Ω, Unless Otherwise Specified. All pin
number references in the figures refer to the 28 lead PLCC package.
CONDITIONS
1% THD, Z
L
= 600Ω, (Note 2, Figure 1)
0 < f < 100Hz (Note 3, Figure 2)
V
TX
19
R
T
600kΩ
E
RX
1V
RMS
0 < f < 100Hz
E
L
C
2.16µF
300Ω
A
R
R
RX
V
R
RING
28
RSN
16
R
RX
300kΩ
LZ
R
= V
R
/A
R
300Ω
PARAMETER
Overload Level
Longitudinal Impedance (Tip/Ring)
TIP
27
R
L
600Ω
I
DCMET
23mA
RING
28
RSN
16
MIN
3.1
-
A
T
V
T
TYP
-
20
TIP
27
MAX
-
35
V
TX
19
UNITS
V
PEAK
Ω/Wire
V
TRO
R
T
600kΩ
300kΩ
LZ
T
= V
T
/A
T
FIGURE 1. OVERLOAD LEVEL (TWO-WIRE PORT)
FIGURE 2. LONGITUDINAL IMPEDANCE
56
HC5515
Electrical Specifications
T
A
= -40
o
C to 85
o
C, V
CC
= +5V
±5%,
V
EE
= -5V
±5%,
V
BAT
= -48V, AGND = BGND = 0V, R
DC1
= R
DC2
= 41.2kΩ,
R
D
= 39kΩ, R
SG
= 0Ω, R
F1
= R
F2
= 0Ω, C
HP
= 10nF, C
DC
= 1.5µF, Z
L
= 600Ω, Unless Otherwise Specified. All pin
number references in the figures refer to the 28 lead PLCC package.
(Continued)
CONDITIONS
MIN
TYP
MAX
UNITS
PARAMETER
LONGITUDINAL CURRENT LIMIT (TIP/RING)
Off-Hook (Active)
On-Hook (Standby), R
L
=
∞
No False Detections, (Loop Current),
LB > 45dB (Note 4, Figure 3A)
No False Detections (Loop Current) (Note 5,
Figure 3B)
368Ω
A
TIP
27
R
D
RSN
16
R
DC1
41.2kΩ
R
DC2
A
C
DC
1.5µF
20
5
-
-
-
-
mA
PEAK
/
Wire
mA
PEAK
/
Wire
368Ω
A
2.16µF
E
L
2.16µF
C
39kΩ
TIP
27
R
D
RSN
16
R
DC1
41.2kΩ
R
DC2
C
DC
1.5µF
C
E
L
2.16µF
39kΩ
-5V
-5V
C
A
368Ω
R
DC
RING
14 41.2kΩ
28
DET
368Ω
RING
R
DC
14 41.2kΩ
28
DET
FIGURE 3A. OFF-HOOK
FIGURE 3. LONGITUDINAL CURRENT LIMIT
OFF-HOOK LONGITUDINAL BALANCE
Longitudinal to Metallic
Longitudinal to Metallic
Metallic to Longitudinal
IEEE 455 - 1985, R
LR
, R
LT
= 368Ω
0.2kHz < f < 4.0kHz (Note 6, Figure 4)
R
LR
, R
LT
= 300Ω, 0.2kHz < f < 4.0kHz
(Note 6, Figure 4)
FCC Part 68, Para 68.310
0.2kHz < f < 1.0kHz
1.0kHz < f < 4.0kHz (Note 7)
Longitudinal to 4-Wire
Metallic to Longitudinal
4-Wire to Longitudinal
R
LT
TIP
27
E
L
C
V
TR
2.16µF
R
RX
R
LR
RING
28
RSN
16
300kΩ
V
TX
19
R
T
600kΩ
2.16µF
V
TX
C
V
L
R
LR
300Ω
FIGURE 3B. ON-HOOK
53
53
50
50
53
50
50
R
LT
300Ω
E
TR
TIP
27
70
70
55
55
70
55
55
-
-
-
-
-
-
-
dB
dB
dB
dB
dB
dB
dB
0.2kHz < f < 4.0kHz (Note 8, Figure 4)
R
LR
, R
LT
= 300Ω, 0.2kHz < f < 4.0kHz
(Note 9, Figure 5)
0.2kHz < f < 4.0kHz (Note 10, Figure 5)
V
TX
19
R
T
600kΩ
R
RX
E
RX
RING
28
RSN
16
300kΩ
FIGURE 4. LONGITUDINAL TO METALLIC AND
LONGITUDINAL TO 4-WIRE BALANCE
2-Wire Return Loss
C
HP
= 20nF
FIGURE 5. METALLIC TO LONGITUDINAL AND 4-WIRE TO
LONGITUDINAL BALANCE
25
27
23
-
-
-
-
-
-
dB
dB
dB
0.2kHz to 0.5kHz (Note 11, Figure 6)
0.5kHz to 1.0kHz (Note 11, Figure 6)
1.0kHz to 3.4kHz (Note 11, Figure 6)
TIP IDLE VOLTAGE
Active, I
L
= 0
Standby, I
L
= 0
RING IDLE VOLTAGE
Active, I
L
= 0
-
-46.5
-
V
-
-
-1.5
<0
-
-
V
V
57
HC5515
Electrical Specifications
T
A
= -40
o
C to 85
o
C, V
CC
= +5V
±5%,
V
EE
= -5V
±5%,
V
BAT
= -48V, AGND = BGND = 0V, R
DC1
= R
DC2
= 41.2kΩ,
R
D
= 39kΩ, R
SG
= 0Ω, R
F1
= R
F2
= 0Ω, C
HP
= 10nF, C
DC
= 1.5µF, Z
L
= 600Ω, Unless Otherwise Specified. All pin
number references in the figures refer to the 28 lead PLCC package.
(Continued)
CONDITIONS
MIN
-
V
BAT
= -52V, R
SG
= 0Ω
Z
L
> 20kΩ, 1% THD (Note 12, Figure 7)
E
G
= 0, Z
L
=
∞
(Note 13, Figure 7)
0.2kHz < f < 03.4kHz
0.3kHz < f < 03.4kHz (Note 14, Figure 7)
43
TYP
>-48
-
MAX
-
47
UNITS
V
V
PARAMETER
Standby, I
L
= 0
TIP-RING Open Loop Metallic Voltage, V
TR
4-WIRE TRANSMIT PORT (V
TX
)
Overload Level
Output Offset Voltage
Output Impedance (Guaranteed by Design)
2-Wire to 4-Wire (Metallic to V
TX
) Voltage Gain
3.1
-60
-
0.98
-
-
5
1.0
-
60
20
1.02
V
PEAK
mV
Ω
V/V
Z
D
TIP
27
R
V
S
R
Z
IN
RING
28
RSN
16
V
M
R
T
600kΩ
E
G
R
RX
300kΩ
V
TX
19
R
L
600Ω
2.16µF
C
V
TR
I
DCMET
23mA
R
RX
RING
28
RSN
16
300kΩ
TIP
27
V
TX
19
R
T
600kΩ
V
TXO
V
TX
Z
L
R
LR
FIGURE 6. TWO-WIRE RETURN LOSS
FIGURE 7. OVERLOAD LEVEL (4-WIRE TRANSMIT PORT),
OUTPUT OFFSET VOLTAGE, 2-WIRE TO 4-WIRE
VOLTAGE GAIN AND HARMONIC DISTORTION
4-WIRE RECEIVE PORT (RSN)
DC Voltage
R
X
Sum Node Impedance (Gtd by Design)
Current Gain-RSN to Metallic
FREQUENCY RESPONSE (OFF-HOOK)
2-Wire to 4-Wire
4-Wire to 2-Wire
4-Wire to 4-Wire
INSERTION LOSS
2-Wire to 4-Wire
4-Wire to 2-Wire
GAIN TRACKING (Ref = -10dBm, at 1.0kHz)
2-Wire to 4-Wire
2-Wire to 4-Wire
2-Wire to 4-Wire
4-Wire to 2-Wire
+3dBm to +7dBm (Note 21, Figure 9)
-40dBm to +3dBm (Note 21, Figure 9)
-55dBm to -40dBm (Note 21, Figure 9)
-40dBm to +7dBm (Note 22, Figure 9)
-0.15
-0.1
-0.2
-0.1
-
-
-
-
0.15
0.1
0.2
0.1
dB
dB
dB
dB
0dBm, 1kHz (Note 19, Figure 9)
0dBm, 1kHz (Note 20, Figure 9)
-0.2
-0.2
-
-
0.2
0.2
dB
dB
0dBm at 1.0kHz, E
RX
= 0V
0.3kHz < f < 3.4kHz (Note 16, Figure 9)
0dBm at 1.0kHz, E
G
= 0V
0.3kHz < f < 3.4kHz (Note 17, Figure 9)
0dBm at 1.0kHz, E
G
= 0V
0.3kHz < f < 3.4kHz (Note 18, Figure 9)
-0.2
-0.2
-0.2
-
-
-
0.2
0.2
0.2
dB
dB
dB
I
RSN
= 0mA
0.2kHz < f < 3.4kHz
0.3kHz < f < 3.4kHz (Note 15, Figure 8)
-
-
900
0
-
1000
-
20
1100
V
Ω
Ratio
58
HC5515
Electrical Specifications
T
A
= -40
o
C to 85
o
C, V
CC
= +5V
±5%,
V
EE
= -5V
±5%,
V
BAT
= -48V, AGND = BGND = 0V, R
DC1
= R
DC2
= 41.2kΩ,
R
D
= 39kΩ, R
SG
= 0Ω, R
F1
= R
F2
= 0Ω, C
HP
= 10nF, C
DC
= 1.5µF, Z
L
= 600Ω, Unless Otherwise Specified. All pin
number references in the figures refer to the 28 lead PLCC package.
FPGA/CPLD
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