HC2510C
HC2510C
Features
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Phase-Locked Loop Clock Distribution for
Synchronous DRAM Applications
Supports PC-100 and Meets “PC100 SDRAM
registered DIMM Specification Rev. 1.2”
Distributes One Clock Input to One Bank of Ten
Outputs
No External RC Network Required
External Feedback (FBIN) Pin is Used to
Synchronize the Outputs to the Clock Input
Separate Output Enable for Each Output Bank
Operates at 3.3 V V
cc
125 MHz Maximum Frequency
On-chip Series Damping Resistors
Support Spread Spectrum Clock(SSC)
Synthesizers
ESD Protection Exceeds 3000 V per MIL-STD-
883, Method 3015 ; Exceeds 350 V Using
Machine
Model ( C = 200 pF, R = 0 )
Latch-Up Performance Exceeds 400 mA per
JESD 17
Packaged in Plastic 24-Pin Thin Shrink Small-
Outline Package
General Description
The HC2510C is a
low-skew, low jitter, phase-
locked loop(PLL) clock driver, distributing high
frequency clock signals for SDRAM.
The HC2510C operates at 3.3V V
cc
and provides
integrated series-damping resistors that make it ideal
for driving point-to-point loads. The propagation delay
from the CLK input to any clock output is nearly zero.
Ten outputs provide low-skew and low-jitter clocks.
All outputs can be enabled or disabled via the control
input(G). Output signal duty cycles are adjusted to 50
percent, independent of the duty cycle at CLK.
The HC2510C is specially designed to interface with
high speed SDRAM applications in the range of
25MHz to 125MHz and includes an internal RC
network which provides excellent jitter characteristics
and eliminates the needs for external components.
For the test purpose, the PLL can be bypassed by
strapping AV
cc
to ground.
The HC2510C is characterized for operation from 0°C
to 85°C.
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Pin Configuration
TSSOP 24 PACKAGE
(TOP VIEW)
AGND
Vcc
1Y0
1Y1
1Y2
GND
GND
1Y3
1Y4
Vcc
G
FBOUT
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
CLK
AVcc
Vcc
1Y9
1Y8
GND
GND
Function Table
INPUTS
G
X
CLK
L
H
H
OUTPUTS
1Y
(0:9)
L
L
H
FBOUT
L
H
H
1Y7
L
1Y6
1Y5
Vcc
FBIN
H
1
HC2510C
Table 1. Pin Description
Pin Name
CLK
FBIN
Pin No.
24
13
Type
I
I
Functional Description
Clock Input. CLK provides the reference signal to the internal
PLL.
Feedback Input. FBIN provides the feedback signal to the
internal PLL.
Output Bank Enable. When G is high, all outputs 1Y(0:9) are
enabled.
When G is low, Outputs 1Y(0:9) are disable to a logic-low
state.
Feedback Output. FBOUT completes the feedback loop of the
PLL by being wired to FBIN.
Clock Outputs. These outputs provide low-skew copies of
CLKIN. Each output has an embedded series-damping
resistor.
Analog Power Supply. AV
cc
provides the power reference for
the analog circuitry. AV
cc
can be also used to bypass the PLL
for the test purpose. When AV
cc
is strapped to ground, PLL is
bypassed and CLK is buffered directly to the device outputs.
Analog Ground. AGND provides the ground reference for the
analog circuitry.
Power Supply
Ground
G
11
I
FBOUT
1Y(0:9)
12
3,4,5,8,9
15,16,17,20,2
1
23
O
O
AV
cc
Power
Groun
d
Power
Groun
d
AGND
V
cc
GND
1
2,10,14,22
6,7,18,19
Table 2. Absolute Maximum Ratings Over Operating Free-air
Temperature Range
Symbols
V
cc
V
I
V
o
I
IK
I
OK
I
o
P
MAX
T
stg
Parameter
Supply Voltage Range
Input Voltage Range
Voltage Range applied to any
input in the high or low state
Input Clamp Current
Output Clamp Current
Continuous Output Current
Maximum Power Dissipaiton
Storage Temperature Range
Value
-0.5 to 4.6
-0.5 to 6.5
-0.5 to Vcc+0.5
±50
±50
±50
0.7
- 65 to 150
Unit
V
V
V
mA
mA
mA
W
°C
Conditions
V
I
<0 or V
I
>V
cc
V
o
<0 or V
o
>V
cc
V
o
=0 to V
cc
3
HC2510C
Table 3. Recommended Operating Conditions
Symbol
AV
CC
V
IH
V
IL
V
I
I
OH
I
OL
T
A
Parameter
Supply Voltage
High-level Input Voltage
Low-level Input Voltage
Input Voltage
High-level Output Current
Low-level Output Current
Operating Free-air Temperature
Value
Min
Max
3
2
0
3.6
0.8
V
CC
-12
12
85
Unit
V
V
V
V
mA
mA
°C
Condition
0
Table 4. Electrical Characteristics Over Recommended Operating Free-air
Temperature Range
Symbol
V
IK
V
OH
Vcc-0.2
2.1
2.4
0.2
0.8
0.55
±5
10
500
4
6
Min
Value
Typ
Max
-1.2
Unit
V
V
AV
CC
(V)
3
Min to Max
3
3
Min to Max
3
3
3.6
3.6
3.3 to 3.6
3.3
3.3
Test Conditions
I
I
= -18mA
I
OH
= -100µA
I
OH
= -12 mA
I
OH
= -6 mA
I
OL
=100 mA
I
OL
= 12 mA
I
OL
= 6 mA
V
I
=V
CC
or GND
V
I
=V
CC
or GND, I
O
= 0,
Ouputs: low or high
One input at V
CC
- 0.6V,
Other Inputs at V
CC
or GND
V
I
= V
CC
or GND
V
O
= V
CC
or GND
V
OL
I
I
I
CC
∆I
CC
V
µA
µA
µA
pF
pF
C
i
C
o
Table 5.Timing Requirements Over Recommended Ranges of Supply Voltage
and Operating free-air Temperature
Symbol
f
clock
Parameter
Clock Frequency
Input Clock Duty Cycle
Stabilization Time♣
Value
Min
25
40
Max
125
60
1
Unit
MHz
%
ms
♣
Time to obtain phase lock of its feedback signal to its reference signal.
4
HC2510C
Table 6. Switching Characteristics Over Recommended Ranges of Supply
Voltage and Operating Free-air Temperature. (C
L
=30
pF
)
=
Parameter
From(Input)
66MHz < CLKIN↑<
100MHz
CLKIN↑ = 100MHz
Any Y of FBOUT
CLKIN
>
66MHz
CLKIN
>
66MHz
TO(Output)
FBIN↑
FBIN↑
Any Y or
FBOUT
Any Y or
FBOUT
Any Y or
FBOUT
Any Y or
FBOUT
Any Y or
FBOUT
V
CC
= 3.3V
V
CC
=
±0.165V
3.3V±0.3V
Unit
Min Typ Max Min Typ Max
150
-50
150
50
200
-100
45
1.3
1.7
1.9
2.5
0.8
1.2
100
55
2.1
2.7
ps
ps
ps
ps
%
ns
ns
t
phase error
♣
t
sk
Jitter
(pk-pk)
Duty
Cycle
t
r
t
f
=
These parameters are not production tested.
♣
Phase error does not include jitter.
Figure 1. Load Circuit and Voltage Waveforms
3V
From Output Under Test
Input
30pF
500
§Ù
tpd
50% V
CC
0V
V
OH
2V
2V
0.4V
50% V
CC
0.4V
Output
tr
tf
V
OL
Load Circuit For Outputs
Voltage Waveforms
Propagation Delay Times
Notes: 1. All input pulses are supplied by generators having
the following characteristics: PRR
≤
100MHz, Z
o
=50Ω, t
r
=1.2ns, t
f
=1.2ns
2.The outputs are measured one at a time with one
transition per measurement.
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stm32/stm8
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