SL74HC165
8-Bit Serial or Parallel-Input/
Serial-Output Shift Register
High-Performance Silicon-Gate CMOS
The SL74HC165 is identical in pinout to the LS/ALS165. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
This device is an 8-bit shift register with complementary outputs
from the last stage. Data may be loaded into the register either in
parallel or in serial form. When the Serial Shift/ Parallel Load input is
low, the data is loaded asynchronously in parallel. When the Serial
Shift/Parallel Load input is high, the data is loaded serially on the rising
edge of either Clock or Clock Inhibit (see the Function Table).
The 2
-input NOR clock may be used either by combining two
independent clock sources or by designating one of the clock inputs to
act as a clock inhibit.
•
Outputs Directly Interface to CMOS, NMOS, and TTL
•
Operating Voltage Range: 2.0 to 6.0 V
•
Low Input Current: 1.0
µA
•
High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION
SL74HC165N Plastic
SL74HC165D SOIC
T
A
= -55° to 125° C for all packages
LOGIC DIAGRAM
PIN ASSIGNMENT
PIN 16=V
CC
PIN 8 = GND
FUNCTION TABLE
Inputs
Serial Shift/
Parallel Load
L
H
H
H
H
H
H
H
L
L
X
H
L
H
X
L
Clock
H
Clock
Inhibit
X
L
L
S
A
X
L
H
L
H
X
X
X
A-H
a...h
X
X
X
X
X
X
X
no change
No Clock
Internal Stages
Q
A
a
L
H
L
H
Q
B
-Q
G
b-g
Q
An
-Q
Fn
Q
An
-Q
Fn
Q
An
-Q
Fn
Q
An
-Q
Fn
no change
Output
Q
H
h
Q
Gn
Q
Gn
Q
Gn
Q
Gn
Serial Shift via Clock
Inhibit
Inhibited Clock
Asynchronous Parallel Load
Serial Shift via Clock
Operation
X = Don’t Care
Q
An
-Q
Fn
= Data shifted from the preceding stage
SLS
System Logic
Semiconductor
SL74HC165
MAXIMUM RATINGS
*
Symbol
V
CC
V
IN
V
OUT
I
IN
I
OUT
I
CC
P
D
Tstg
T
L
*
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Current, per Pin
DC Supply Current, V
CC
and GND Pins
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
Value
-0.5 to +7.0
-1.5 to V
CC
+1.5
-0.5 to V
CC
+0.5
±20
±25
±50
750
500
-65 to +150
260
Unit
V
V
V
mA
mA
mA
mW
°C
°C
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
IN
, V
OUT
T
A
t
r
, t
f
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time (Figure 1)
V
CC
=2.0 V
V
CC
=4.5 V
V
CC
=6.0 V
Min
2.0
0
-55
0
0
0
Max
6.0
V
CC
+125
1000
500
400
Unit
V
V
°C
ns
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V
IN
and V
OUT
should be constrained to the range
GND≤(V
IN
or V
OUT
)≤V
CC
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V ).
CC
Unused outputs must be left open.
SLS
System Logic
Semiconductor
SL74HC165
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
V
CC
Symbol
Parameter
Test Conditions
V
Guaranteed Limit
25
°C
to
-55°C
1.5
3.15
4.2
0.3
0.9
1.2
1.9
4.4
5.9
3.98
5.48
0.1
0.1
0.1
0.26
0.26
±0.1
8.0
≤85
°C
1.5
3.15
4.2
0.3
0.9
1.2
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.33
0.33
±1.0
80
≤125
°C
1.5
3.15
4.2
0.3
0.9
1.2
1.9
4.4
5.9
3.7
5.2
0.1
0.1
0.1
0.4
0.4
±1.0
160
µA
µA
V
Unit
V
IH
Minimum High-Level
Input Voltage
Maximum Low -Level
Input Voltage
Minimum High-Level
Output Voltage
V
OUT
=0.1 V or V
CC
-0.1 V
I
OUT
≤
20
µA
V
OUT
=0.1 V or V
CC
-0.1 V
I
OUT
≤
20
µA
V
IN
=V
IH
or V
IL
I
OUT
≤
20
µA
V
IN
=V
IH
or V
IL
I
OUT
≤
4.0 mA
I
OUT
≤
5.2 mA
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
6.0
6.0
V
V
IL
V
V
OH
V
V
OL
Maximum Low-Level
Output Voltage
V
IN
= V
IL
or V
IH
I
OUT
≤
20
µA
V
IN
= V
IL
or V
IH
I
OUT
≤
4.0 mA
I
OUT
≤
5.2 mA
I
IN
I
CC
Maximum Input
Leakage Current
Maximum Quiescent
Supply Current
(per Package)
V
IN
=V
CC
or GND
V
IN
=V
CC
or GND
I
OUT
=0µA
SLS
System Logic
Semiconductor
SL74HC165
AC ELECTRICAL CHARACTERISTICS
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
Symbol
f
max
Parameter
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 8)
Maximum Propagation Delay, Clock (or Clock
Inhibit) to Q
H
or Q
H
(Figures 1 and 8)
Maximum Propagation Delay , SerialShift./.Parallel
Load to Q
H
or Q
H
(Figures 2 and 8)
Maximum Propagation Delay, Input H to Q
H
or Q
H
(Figures 3 and 8)
Maximum Output Transition Time, Any Output
(Figures 1 and 8)
Maximum Input Capacitance
Power Dissipation Capacitance (Per Package)
C
PD
Used to determine the no-load dynamic power
consumption:
P
D
=C
PD
V
CC2
f+I
CC
V
CC
V
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
-
Guaranteed Limit
25
°C
to
-55°C
6.0
30
35
150
30
26
175
35
30
150
30
26
75
15
13
10
≤85°C
4.8
24
28
190
38
33
220
44
37
190
38
33
95
19
16
10
≤125°C
4.0
20
24
225
45
38
265
53
45
225
45
38
110
22
19
10
Unit
MHz
t
PLH
, t
PHL
ns
t
PLH
, t
PHL
ns
t
PLH
, t
PHL
ns
t
TLH
, t
THL
ns
C
IN
pF
Typical @25°C,V
CC
=5.0 V
85
pF
SLS
System Logic
Semiconductor
SL74HC165
TIMING REQUIREMENTS
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
Symbol
t
SU
Parameter
Minimum Setup Time, Parallel
Data Inputs to Serial
Shift/Parallel Load (Figure 4)
Minimum Setup Time, Input S
A
to Clock (or Clock Inhibit)
(Figure 5)
Minimum Setup Time, Serial
Shift/Parallel Load to Clock (or
Clock Inhibit) (Figure 6)
Minimum Setup Time, Clock to
Clock Inhibit (Figure 7)
Minimum Hold Time, Serial
Shift/Parallel Load to Parallel
Data Inputs (Figure 4)
Minimum Hold Time, Clock (or
Clock Inhibit) to Input S
A
(Figure 5)
Minimum Hold Time, Clock (or
Clock Inhibit) to Serial
Shift/Parallel Load (Figure 6)
Minimu m Recovery Time,
Clock to Clock Inhibit
(Figure 7)
Minimum Pulse Width, Clock
(or Clock Inhibit) (Figure 1)
Minimum Pulse Width, Serial
Shift/Parallel Load (Figure 2)
Maximum Input Rise and Fall
Times (Figure 1)
V
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
25
°C
to
-55°C
100
20
17
100
20
17
100
20
17
100
20
17
5
5
5
5
5
5
5
5
5
100
20
17
80
16
14
80
16
14
1000
500
400
Guaranteed Limit
≤85°C
125
25
21
125
25
21
125
25
21
125
25
21
5
5
5
5
5
5
5
5
5
125
25
21
100
20
17
100
20
17
1000
500
400
≤125°C
150
30
26
150
30
26
150
30
26
150
30
26
5
5
5
5
5
5
5
5
5
150
30
26
120
24
20
120
24
20
1000
500
400
Unit
ns
t
SU
ns
t
SU
ns
t
SU
ns
t
h
ns
t
h
ns
t
h
ns
t
rec
ns
t
w
ns
t
w
ns
t
r,
t
f
ns
SLS
System Logic
Semiconductor
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