CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER
Sampling Rate
Supply Current
Logic ‘1’ Input
Logic ‘0’ Input
Logic ‘1’ Output
Logic ‘0’ Output
Clock Duty Cycle
Audio Input Voltage
Audio Output Voltage
Audio Input Impedance
Audio Output Impedance
Transfer Gain
Syllabic Filter Time Constant
Signal Estimate Filter Time
Constant
Enc Threshold
Minimum Step Size
Quieting Pattern Amplitude
AGC Threshold
Clamping Threshold
Unless Otherwise Specified, typical parameters are at 25
o
C, Min-Max are over operating temperature
ranges. V
DD
= 5.0V, Sampling Rate = 16Kbps, AG = DG = 0V, A
IN
= 1.2V
RMS
SYMBOL
CLK
I
DD
V
IH
V
IL
V
OH
V
OL
A
IN
A
OUT
Z
IN
Z
OUT
A
E-D
t
SF
t
SE
Note 3
Note 3
Note 4
Note 4
AC Coupled (Note 5)
AC Coupled (Note 6)
Note 7
Note 7
No Load, Audio In to Audio Out.
Note 8
Note 8
AIN at 100Hz (Note 9), (Typ) 0.3% = 15mV
RMS
MSS
V
QP
V
ATH
V
CTH
Note 10
FZ = 0V or APT = 0V (Note 11)
Note 12
Note 13
Note 2
CONDITIONS
MIN
9
-
3.5
-
4.0
-
30
-
-
-
-
-2.0
-
1.0
-
-
-
-
-
TYP
16
0.3
-
-
-
-
-
0.5
0.5
280
150
-
4.0
-
6
0.1
10
0.1
0.75
MAX
64
1.5
-
1.5
-
0.4
70
1.2
1.2
-
-
+2.0
-
-
-
-
-
-
-
UNITS
kbps
mA
V
V
V
V
%
V
RMS
V
RMS
kΩ
kΩ
dB
ms
ms
mV
PEAK
%V
DD
mV
P-P
F.S.
F.S.
NOTES:
2. There is one NRZ (Non-Return Zero) data bit per clock period. Data is clocked out on the negative clock edge. Data is clocked into the
CVSD on the positive going edge (see Figure 2). Clock may be run at less than 9kbps and greater than 64kbps.
3. Logic inputs are CMOS compatible at supply voltage and are diode protected. Digital data input is NRZ at clock rate.
4. Logic outputs are CMOS compatible at supply voltage and will withstand short-circuits to V
DD
or ground. Digital data output is NRZ and
changes with negative clock transitions. Each output will drive one LS TTL load.
5. Recommended voice input range for best voice performance. Should be externally AC coupled.
6. May be used for side-tone in encode mode. Should be externally AC coupled. Varies with audio input level by
±2dB.
7. Presents series impedance with audio signal. Zero signal reference is approximately V
DD
/2.
8. Note that filter time constants are inversely proportional to clock rate. Both filters approximate single pole responses.
9. The minimum audio input voltage above which encoding takes place.
10. The minimum audio output voltage change that can be produced by the internal DAC.
11. Settled value, the “quieting” pattern or idle-channel audio output steps at one-half the bit rate, changing state on negative clock transitions.
12. A logic “0” will appear at the AGC output pin when the recovered signal reaches one-half of full-scale value (positive or negative), i.e., at
V
DD
/2
±25%
of V
DD
.
13. The recovered signal will be clamped, and the computation will be inhibited, when the recovered signal reaches three-quarters of full-
scale value, and will unclamp when it falls below this value (positive or negative).
2
HC-55564
Pin Descriptions
PIN NUMBER
14 LEAD DIP
1
2
3
SYMBOL
V
DD
Analog GND
A
OUT
DESCRIPTION
Positive Supply Voltage. Voltage range is 4.5V to 6.0V.
Analog Ground connection to D/A ladders and comparator.
Audio Out recovered from 10-bit DAC. May be used as side tone at the transmitter. Presents
approximately 150kΩ source with DC offset of V
DD
/2. Within
±2dB
of Audio Input. Should be ex-
ternally AC coupled.
Automatic Gain Control output. A logic low level will appear at this output when the recovered
signal excursion reaches one-half of full scale value. In each half cycle full scale is V
DD
/2. The
mark-space ratio is proportional to the average signal level.
Audio Input to comparator. Should be externally AC coupled. Presents approximately 280kΩ in
series with V
DD
/2.
No internal connection is made to these pins.
Logic ground. 0V reference for all logic inputs and outputs.
Sampling rate clock. In the decode mode, must be synchronized with the digital input data such
that the data is valid at the positive clock transition. In the encode mode, the digital data is clocked
out on the negative going clock transition. The clock rate equals the data rate.
A single CVSD can provide half-duplex operation. The encode or decode function is selected by the
logic level applied to this input. A low level selects the encode mode, a high level the decode mode.
Alternate Plain Text input. Activating this input caused a digital quieting pattern to be transmitted, how-
ever; internally the CVSD is still functional and a signal is still available at the A
OUT
port. Active low.
Input for the received digital NRZ data.
Force Zero input. Activating this input resets the internal logic and forces the digital output and the
recovered audio output into the “quieting” condition. An alternating 1-0 pattern appears at the
digital output at 1/2 the clock rate. When this is decoded by a receive CVSD, a 10mV
P-P
inaudible
signal appears at audio output. Active low.
Output for transmitted digital NRZ data.
4
AGC
5
6, 7
8
9
A
IN
NC
Digital GND
Clock
10
11
12
13
Encode/
Decode
APT
Digital In
FZ
14
NOTE:
Digital Out
14. No active input should be left in a “floating condition.”
Functional Diagram
(1)
V
DD
(DIP Pin Numbers Shown)
(12)
DIGITAL
IN
V
DD
2
(10)
ENC/DEC
(9)
CLOCK
(8)
(11) (13) FORCE
APT
ZERO
RESET
T
D
DIGITAL
GND
(14)
DIGITAL
OUT
3V TO 6V
F/F
Q
(5)
A
IN
Z
IN
(2)
ANALOG
GND
COMPARATOR
3 BIT
SHIFT
REGISTER
10 BIT
DAC
10
10
RESET
STEP
SIZE
LOGIC
(3) A
OUT
(SIDE TONE)
Z
OUT
(4) AGC OUT
SIGNAL
ESTIMATE
FILTER 1msec
6
DIGITAL
MODULATOR
±1
SYLLABIC
FILTER
4ms
10 BIT
DAC
RESET
3
HC-55564
Timing Waveforms
SAMPLING CLOCK
FZ/APT
DEC/ENC
DIGITAL NRZ IN
t
DS
DIGITAL NRZ OUT
1
0
1
0
t
DS
: DATA SET UP TIME 100ns TYPICAL
0
1
1
FIGURE 2. CVSD TIMING DIAGRAM
Interface Circuit for HC-55564 CVSD
AUDIO SOURCE
TP3040
INPUT
LEVEL ADJUST
R
A
, R
B
, C
A
OPTIONAL
C
A
R
A
5V
-5V
R
C
1
2
3
4
R
B
5
9
8
VF
X
1+
VF
X
1-
GS
X
VF
R
0
PWRI
V
CC
V
BB
GNDA
0.1µ
0.1µ
15
CLK
12
CLK0
PDN
GNDD
PWR0+
VF
X
0
VF
R
I
(DIP Pin Numbers Shown)
HC-55564
6
16
10
0.1µ
0.1µ
R
D
(NOTE)
1
14
13
11
EXTERNAL
CONTROL
0.1µ
8
AUDIO OUT
5
3
A
IN
A
OUT
4
AGC
D
OUT
D
IN
FZ
V
DD
APT
E/D
14
12
13
11
10
EXTERNAL
CONTROL
(TO DATA I/F)
(FROM DATA I/F)
DIGITAL ANALOG
GND
GND
CLK
9
2
÷
n
CLK GEN
NOTE: R
D
= 100kΩ to 1MΩ
only to Pin 2.
CVSD Hookup for Evaluation
The circuit in Figure 3 is sufficient to evaluate the voice qual-
ity of the CVSD, since when encoding, the feedback signal at
the audio output pin is the reconstructed audio input signal.
CVSD design considerations are as follows:
1. Care should be taken in layout to maintain isolation
between analog and digital signal paths for proper noise
consideration.
2. Power supply decoupling is necessary as close to the
device as possible. A 0.1µF should be sufficient.
3. Ground, then power, must be present before any input sig-
nals are applied to the CVSD. Failure to observe this may
cause a latchup condition which may be destructive.
Latchup may be removed by cycling the power off/on. A
power-up reset circuit may be used that strobes Force
Zero (Pin 13) during power-up as follows:
4. Analog (signal) ground (Pin 2) should be externally tied to
Digital GND (Pin 8) and power supply ground. It is recom-
mended that the A
IN
and A
OUT
ground returns connect
5. Digital inputs and outputs are compatible with standard
CMOS logic using the same supply voltage. All unused
logic inputs must be tied to the appropriate logic level for
desired operation. It is recommended that unused inputs
tied high be done so through a pull-up resistor (1kΩ to
10kΩ). TTL outputs will require 1kΩ pull-up resistors. Pins
4 and 14 will each drive CMOS logic or one low power TTL
input.
6. Since the Audio Out pins are internally DC biased to V
DD
/2,
AC coupling is required. In general, a value of 0.1µF is suffi-
cient for AC coupling of the CVSD audio pins to a filter circuit.
7. The AGC output may be externally integrated to drive an
AGC pre-amp, or it could drive an LED indicator through a
buffer to indicate proper speaking volume.
V
DD
R
(13)
C
FZ
4
HC-55564
Figures 4, 5, and 6 illustrate the typical frequency
response of the HC-55564 for varying input levels and for
varying sampling rates. To prevent slope overload (slew
limiting), the 0dB boundary should not be exceeded. The
frequency response is directly proportional to the sampling
clock rate. The flat bandwidth at 0dB doubles for every
doubling in sampling rate. The output levels were mea-
sured in the encode mode, without filtering, from A
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