HB288800A5/HB288640A5
HB288448A5/HB288320A5
HB288256A5/HB288192A5
HB288160A5/HB288128A5
HB288096A5/HB288064A5
HB288032A5
FLASH ATA Card
800 MByte/640 MByte/448 MByte/320 MByte
256 MByte/192 MByte/160 MByte/128 MByte
96 MByte/64 MByte/32 MByte
ADE-203-952D (Z)
Rev. 3.0
Oct. 2, 2000
Description
HB288800A5, HB288640A5, HB288448A5, HB288320A5, HB288256A5, HB288192A5, HB288160A5,
HB288128A5, HB288096A5, HB288064A5, HB288032A5 are Flash ATA card. This card complies with PC
card ATA standard and is suitable for the usage of data storage memory medium for PC or any other electric
equipment. This card is equipped with Hitachi 256 Mega bit Flash memory. This card is suitable for ISA
(Industry Standard Architecture) bus interface standard , and read/write unit is 1 sector (512 bytes) sequential
access. By using this card it is possible to operate good performance for the system which have PC card slots.
Features
•
PC card ATA standard specification
68 pin two pieces connector and Type II (5 mm)
•
3.3 V/5 V single power supply operation
•
ISA standard and Read/Write unit is 512 bytes (sector) sequential access
Sector Read/Write transfer rate: 8MB/sec burst
HB288800/640/448/320/256/192/160/128/096/064/032A5
•
Card density is 800 Mega bytes maximum
This card is equipped Hitachi 256 Mega bit Flash memory
•
3 variations of mode access
Memory card mode
I/O card mode
True IDE mode
•
Internal self-diagnostic program operates at V
CC
power on
•
High reliability based on internal ECC (Error Correcting Code) function
•
Data write is 300,000 cycles
•
Data reliability is 1 error in 10
–14
bits read.
•
Auto Sleep Function
Card Line Up*
1
Type No.
HB288800A5
HB288640A5
HB288448A5
HB288320A5
HB288256A5
HB288192A5
HB288160A5
HB288128A5
HB288096A5
HB288064A5
HB288032A5
Notes: 1.
2.
3.
4.
Card density Capacity*
800 MB
640 MB
448 MB
320 MB
256 MB
192 MB
160 MB
128 MB
96 MB
64 MB
32 MB
4
Total sectors/ Sectors/
card*
3
track*
2
63
63
63
56
48
32
32
32
32
32
32
Number of
head
16
16
15
15
15
15
10
8
8
4
4
Number of
cylinder
1552
1241
927
745
695
782
978
978
732
978
489
800,980,992 byte 1,564,416
640,475,136 byte 1,250,928
448,519,680 byte 876,015
320,409,600 byte 625,800
256,204,800 byte 500,400
192,184,320 byte 375,360
160,235,520 byte 312,960
128,188,416 byte 250,368
95,944,704 byte
64,094,208 byte
32,047,104 byte
187,392
125,184
62,592
These data are written in ID.
Total tracks = number of head
×
number of cylinder.
Total sectors/card = sectors/track
×
number of head
×
number of cylinder.
It is the logical address capacity including the area which is used for file system.
2
HB288800/640/448/320/256/192/160/128/096/064/032A5
Card Pin Assignment
Memory card mode
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
Signal name
GND
D3
D4
D5
D6
D7
-CE1
A10
-OE
—
A9
A8
—
—
-WE
RDY/-BSY
VCC
—
—
—
—
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
WP
I/O
—
I/O
I/O
I/O
I/O
I/O
I
I
I
—
I
I
—
—
I
O
—
—
—
—
—
I
I
I
I
I
I
I
I
I/O
I/O
I/O
O
I/O card mode
Signal name
GND
D3
D4
D5
D6
D7
-CE1
A10
-OE
—
A9
A8
—
—
-WE
-IREQ
VCC
—
—
—
—
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
-IOIS16
I/O
—
I/O
I/O
I/O
I/O
I/O
I
I
I
—
I
I
—
—
I
O
—
—
—
—
—
I
I
I
I
I
I
I
I
I/O
I/O
I/O
O
True IDE mode
Signal name
GND
D3
D4
D5
D6
D7
-CE1
A10
-ATASEL
—
A9
A8
—
—
-WE
INTRQ
VCC
—
—
—
—
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
-IOIS16
I/O
—
I/O
I/O
I/O
I/O
I/O
I
I
I
—
I
I
—
—
I
O
—
—
—
—
—
I
I
I
I
I
I
I
I
I/O
I/O
I/O
O
3
HB288800/640/448/320/256/192/160/128/096/064/032A5
Memory card mode
Pin No.
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
Signal name
GND
GND
-CD1
D11
D12
D13
D14
D15
-CE2
-VS1
-IORD
-IOWR
—
—
—
—
—
VCC
—
—
—
—
-CSEL
-VS2
RESET
-WAIT
-INPACK
-REG
BVD2
BVD1
D8
D9
D10
-CD2
GND
I/O
—
—
O
I/O
I/O
I/O
I/O
I/O
I
O
I
I
—
—
—
—
—
—
—
—
—
—
I
O
I
O
O
I
I/O
I/O
I/O
I/O
I/O
O
—
I/O card mode
Signal name
GND
GND
-CD1
D11
D12
D13
D14
D15
-CE2
-VS1
-IORD
-IOWR
—
—
—
—
—
VCC
—
—
—
—
-CSEL
-VS2
RESET
-WAIT
-INPACK
-REG
-SPKR
-STSCHG
D8
D9
D10
-CD2
GND
I/O
—
—
O
I/O
I/O
I/O
I/O
I/O
I
O
I
I
—
—
—
—
—
—
—
—
—
—
I
O
I
O
O
I
I/O
I/O
I/O
I/O
I/O
O
—
True IDE mode
Signal name
GND
GND
-CD1
D11
D12
D13
D14
D15
-CE2
-VS1
-IORD
-IOWR
—
—
—
—
—
VCC
—
—
—
—
-CSEL
-VS2
-RESET
IORDY
-INPACK
-REG
-DASP
-PDIAG
D8
D9
D10
-CD2
GND
I/O
—
—
O
I/O
I/O
I/O
I/O
I/O
I
O
I
I
—
—
—
—
—
—
—
—
—
—
I
O
I
O
O
I
I/O
I/O
I/O
I/O
I/O
O
—
4
HB288800/640/448/320/256/192/160/128/096/064/032A5
Card Pin Explanation
Signal name
Direction Pin No.
Description
A10 to A0
I
(PC Card Memory mode)
A10 to A0
(PC Card I/O mode)
A2 to A0
(True IDE mode)
BVD1
I/O
(PC Card Memory mode)
-STSCHG
(PC Card I/O mode)
-PDIAG
(True IDE mode)
BVD2
I/O
(PC Card Memory mode)
-SPKR
(PC Card I/O mode)
-DASP
(True IDE mode)
-CD1, -CD2
O
(PC Card Memory mode)
-CD1, -CD2
(PC Card I/O mode)
-CD1, -CD2
(True IDE mode)
-CE1, -CE2
I
(PC Card Memory mode)
Card Enable
-CE1, -CE2
(PC Card I/O mode)
Card Enable
-CE1, -CE2
(True IDE mode)
-CE2 is used for select the Alternate Status Register
and the Device Control Register while -CE1 is the chip
select for the other task file registers.
7, 42
-CE1 and -CE2 are low active card select signals.
Byte/Word/Odd byte mode are defined by combination
of -CE1, -CE2 and A0.
36, 67
62
27, 28, 29
63
Address bus is A10 to A0. Only A2 to A0 are used,
A10 to A3 should be grounded by the host.
BVD1 outputs the battery voltage status in the card.
This output line is constantly driven to a high state
since a battery is not required for this product.
-STSCHG is used for changing the status of
Configuration and status register in attribute area.
-PDIAG is the Pass Diagnostic signal in Master/Slave
handshake protocol.
BVD2 outputs the battery voltage status in the card.
This output line is constantly driven to a high state
since a battery is not required for this product.
-SPKR outputs speaker signals. This output line is
constantly driven to a high state since this product
does not support the audio function.
-DASP is the Disk Active/Slave Present signal in the
Master/Slave handshake protocol.
-CD1 and -CD2 are the card detection signals. -CD1
and -CD2 are connected to ground in this card, so
host can detect that the card is inserted or not.
8, 11, 12, 22, 23, Address bus is A10 to A0. A10 is MSB and A0 is
LSB.
24, 25, 26, 27,
28, 29
5
微控制器 MCU
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
