74HC4040-Q100;
74HCT4040-Q100
12-stage binary ripple counter
Rev. 1 — 24 March 2014
Product data sheet
1. General description
The 74HC4040-Q100; 74HCT4040-Q100 is a 12-stage binary ripple counter with a clock
input (CP), an overriding asynchronous master reset input (MR) and twelve parallel
outputs (Q0 to Q11). The counter advances on the HIGH-to-LOW transition of CP. A
HIGH on MR clears all counter stages and forces all outputs LOW, independent of the
state of CP. Each counter stage is a static toggle flip-flop. Inputs include clamp diodes that
enable the use of current limiting resistors to interface inputs to voltages in excess of V
CC
.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
Complies with JEDEC standard no. 7A
Input levels:
For 74HC4040-Q100: CMOS level
For 74HCT4040-Q100: TTL level
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0
)
Multiple package options
3. Applications
Frequency dividing circuits
Time delay circuits
Control counters
Nexperia
74HC4040-Q100; 74HCT4040-Q100
12-stage binary ripple counter
4. Ordering information
Table 1.
Ordering information
Package
Temperature range
74HC4040D-Q100
74HCT4040D-Q100
74HC4040DB-Q100
74HCT4040DB-Q100
74HC4040PW-Q100
74HCT4040PW-Q100
74HC4040BQ-Q100
74HCT4040BQ-Q100
40 C
to +125
C
40 C
to +125
C
TSSOP16
40 C
to +125
C
SSOP16
40 C
to +125
C
Name
SO16
Description
plastic small outline package; 16 leads; body
width 3.9 mm
plastic shrink small outline package; 16 leads;
body width 5.3 mm
plastic thin shrink small outline package; 16
leads; body width 4.4 mm
Version
SOT109-1
SOT338-1
SOT403-1
SOT763-1
Type number
DHVQFN16 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 16
terminals; body 2.5
3.5
0.85 mm
5. Functional diagram
CP
MR
10
11
T
12-STAGE COUNTER
C
D
9
7
6
5
3
2
4
13
12
14
15
1
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11
001aad589
Fig 1.
Functional diagram
CTR12
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
9
7
6
5
3
2
4
13
12
14
15
1
10
11
+
CT = 0
0
9
7
6
5
3
2
4
13
12
14
15
1
10
CP
CT
11
MR
11
001aad585
001aad586
Fig 2.
Logic symbol
Fig 3.
IEC logic symbol
74HC_HCT4040_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 1 — 24 March 2014
2 of 19
Nexperia
74HC4040-Q100; 74HCT4040-Q100
12-stage binary ripple counter
CP
FF
T 1
Q
FF
T 2
Q
FF
T 3
Q
FF
T 4
Q
FF
T 5
Q
FF
T 6
Q
Q
RD
MR
RD
Q
RD
Q
RD
Q
RD
Q
RD
Q
Q0
Q1
Q2
Q3
Q4
Q5
FF
T 7
Q
FF
T 8
Q
FF
T 9
Q
FF
T 10
Q
FF
T 11
Q
FF
T 12
Q
Q
RD
RD
Q
RD
Q
RD
Q
RD
Q
RD
Q
Q6
Q7
Q8
Q9
Q10
Q11
001aad588
Fig 4.
Logic diagram
74HC_HCT4040_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 1 — 24 March 2014
3 of 19
Nexperia
74HC4040-Q100; 74HCT4040-Q100
12-stage binary ripple counter
6. Pinning information
6.1 Pinning
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 5.
Pin configuration SO16, SSOP16 and
TSSOP16
Fig 6.
Pin configuration DHVQFN16
6.2 Pin description
Table 2.
Symbol
Q11
Q5
Q4
Q6
Q3
Q2
Q1
GND
Q0
CP
MR
Q8
Q7
Q9
Q10
V
CC
74HC_HCT4040_Q100
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Description
output 11
output 5
output 4
output 6
output 3
output 2
output 1
ground (0 V)
output 0
clock input (HIGH-to-LOW, edge-triggered)
master reset input (active HIGH)
output 8
output 7
output 9
output 10
positive supply voltage
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 1 — 24 March 2014
4 of 19
Nexperia
74HC4040-Q100; 74HCT4040-Q100
12-stage binary ripple counter
7. Functional description
7.1 Function table
Table 3.
Input
CP
X
[1]
Function table
Output
MR
L
L
H
Q0 to Q11
no change
count
L
H = HIGH voltage level; L = LOW voltage level; X = don’t care;
= LOW-to-HIGH clock transition;
= HIGH-to-LOW clock transition.
7.2 Timing diagram
1
CP input
MR input
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
001aad587
2
4
8
16
32
64
128
256
512 1024 2048 4096
Fig 7.
Timing diagram
74HC_HCT4040_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 1 — 24 March 2014
5 of 19
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