Operating Temperature Range ........................... -40NC to +85NC
Junction Temperature ......................................................+150NC
Storage Temperature Range ............................ -65NC to +150NC
Lead Temperature (soldering, 10s) ................................. +300NC
Soldering Temperature (reflow) .......................................+260NC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
Package Thermal Characteristics
(Note 1)
TDFN
Junction-to-Ambient Thermal Resistance (q
JA
).......59.3NC/W
Junction-to-Case Thermal Resistance (q
JC
) ...........22.5NC/W
Note 1:
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to
www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics
(V
DD
= 4.75V to 5.25V, V
OVDD
= 2.3V to 5.25V, f
SAMPLE
= 500ksps, Reference Mode 3, V
REF
= 4.096V; T
A
= T
MIN
to T
MAX
, unless
otherwise noted. Typical values are at T
A
= +25NC.) (Note 2)
PARAMETER
ANALOG INPUT (Note 3)
Input Voltage Range
AIN+ to AIN-, K =
AIN+ to GND
AIN- to GND
Input Leakage Current
Input Capacitance
Input-Clamp Protection Current
STATIC PERFORMANCE (Note 4)
Resolution
No Missing Codes
Offset Error
Offset Error Temperature
Coefficient
Gain Error
Gain Error Temperature
Coefficient
Integral Nonlinearity
Differential Nonlinearity
Positive Full-Scale Error
Analog Input CMRR
CMRR
INL
DNL
Guaranteed by design
-1.5
-0.5
-5.5
-1.96
-3.9
N
16
16
-4.0
±1
±0.006
±1.4
±0.008
±0.5
±0.2
+1.5
+0.5
+5.5
+3.9
+4.0
Bits
Bits
mV
LSB/°C
LSB
LSB/°C
LSB
LSB
LSB
LSB/V
Both inputs
-20
Acquisition phase
SYMBOL
CONDITIONS
MIN
TYP
MAX
+K x
V
REF
+(V
DD
+ 0.1)
+0.1
+0.001
32
+20
+10
µA
pF
mA
UNITS
5.000
4.096
0
-0.1
-0.1
-10
V
Absolute Input Voltage Range
V
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Maxim Integrated
│
2
MAX11164
16-Bit, 500ksps, 0 to 5V SAR ADC with
Internal Reference in TDFN
Electrical Characteristics (continued)
(V
DD
= 4.75V to 5.25V, V
OVDD
= 2.3V to 5.25V, f
SAMPLE
= 500ksps, Reference Mode 3, V
REF
= 4.096V; T
A
= T
MIN
to T
MAX
, unless
otherwise noted. Typical values are at T
A
= +25NC.) (Note 2)
PARAMETER
Power-Supply Rejection (Note 5)
Transition Noise
REFERENCE (Note 7)
REF Output Initial Accuracy
REF Output Temperature
Coefficient
REFIO Output Initial Accuracy
REFIO Output Temperature
Coefficient
REFIO Output Impedance
REFIO Input Voltage Range
Reference Buffer Initial Offset
Reference Buffer Offset Drift
External Compensation Capacitor
REF Voltage Input Range
REF Input Capacitance
REF Load Current
DYNAMIC PERFORMANCE (Note 6)
VREF = 4.096V, reference mode 3
VREF = 4.096V, reference mode 1
VREF = 2.5V, reference mode 3
Internal reference, reference mode 0
VREF = 4.096V, reference mode 3
VREF = 4.096V, reference mode 1
VREF = 2.5V, reference mode 3
Internal reference, reference mode 0
99
90.5
91
92.2
92.0
89.2
92.0
92.0
91.8
89.0
91.9
106.8
-104.0
-119.4
-96.8
dB
dB
dB
dB
dB
I
REF
C
EXT
V
REF
V
REF
TC
REF
V
REFIO
TC
REFIO
Reference mode 0
Reference mode 0
Reference modes 0 and 2
Reference modes 0 and 2
Reference modes 0 and 2
Reference mode 1
Reference mode 0 and 1
Reference mode 0 and 1
Required for reference modes 0 and 1,
recommended for reference modes 2 and 3
Reference modes 2 and 3
Reference modes 2 and 3
V
REF
= 4.096V,
reference modes 2 and 3
3
-500
-12
10
2.5
20
137
4.25
±5.6
4.092
-17
4.092
-15
4.096
±9
4.096
±6
10
4.096
4.25
+500
+12
4.100
+17
4.100
+15
V
ppm/°C
V
ppm/°C
kΩ
V
µV
µV/°C
µF
V
pF
µA
SYMBOL
PSR
CONDITIONS
MIN
TYP
-5.7
0.5
MAX
UNITS
LSB/V
LSB
RMS
Signal-to-Noise Ratio
SNR
Signal-to-Noise Plus Distortion
(Note 7)
Spurious-Free Dynamic Range
Total Harmonic Distortion
Intermodulation Distortion
(Note 8)
SINAD
SFDR
THD
IMD
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Maxim Integrated
│
3
MAX11164
16-Bit, 500ksps, 0 to 5V SAR ADC with
Internal Reference in TDFN
Electrical Characteristics (continued)
(V
DD
= 4.75V to 5.25V, V
OVDD
= 2.3V to 5.25V, f
SAMPLE
= 500ksps, Reference Mode 3, V
REF
= 4.096V; T
A
= T
MIN
to T
MAX
, unless
otherwise noted. Typical values are at T
A
= +25NC.) (Note 2)
PARAMETER
SAMPLING DYNAMICS
Throughput Sample Rate
Transient Response
Full-Power Bandwidth
Aperture Delay
Aperture Jitter
POWER SUPPLIES
Analog Supply Voltage
Interface Supply Voltage
Analog Supply Current
V
DD
Shutdown Current
Interface Supply Current (Note 9)
OVDD Shutdown Current
V
DD
= 5V, V
OVDD
= 3.3V,
reference mode = 2, 3
V
DD
= 5V, V
OVDD
= 3.3V,
reference mode = 0, 1
0.7 x
V
OVDD
0.3 x
V
OVDD
±0.05 x V
OVDD
10
V
IN
= 0V or V
OVDD
I
SOURCE
= 2mA
I
SINK
= 2mA
-10
15
t
CYC
t
CONV
t
ACQ
t
CNVPW
CNVST rising to data available
t
ACQ
= t
CYC
- t
CONV
CS
mode
2
1.3
0.5
5
1.5
-10
V
OVDD
-
0.4
0.4
+10
+10
I
OVDD
V
OVDD
= 2.3V
V
OVDD
= 5.25V
V
DD
V
OVDD
I
VDD
Reference modes 0 and 1
Reference modes 2 and 3
4.75
2.3
5.0
2.9
5.7
3.2
0.01
1.5
4.0
0.08
23.7
mW
33.3
5.25
5.25
6.75
3.5
10
2.0
5.0
10
V
V
mA
µA
mA
µA
Full-scale step
-3dB point
-0.1dB point
6
> 0.2
2.5
< 50
500
400
ksps
ns
MHz
ns
ps
RMS
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Power Dissipation
DIGITAL INPUTS (DIN, SCLK, CNVST)
Input Voltage High
Input Voltage Low
Input Hysteresis
Input Capacitance
Input Current
DIGITAL OUTPUT (DOUT)
Output Voltage High
Output Voltage Low
Three-State Leakage Current
Three-State Output Capacitance
TIMING (Note 9)
Time Between Conversions
Conversion Time
Acquisition Time
CNVST Pulse Width
µs
µs
µs
ns
V
OH
V
OL
V
V
µA
pF
V
IH
V
IL
V
HYS
C
IN
I
IN
V
V
V
pF
µA
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Maxim Integrated
│
4
MAX11164
16-Bit, 500ksps, 0 to 5V SAR ADC with
Internal Reference in TDFN
Electrical Characteristics (continued)
(V
DD
= 4.75V to 5.25V, V
OVDD
= 2.3V to 5.25V, f
SAMPLE
= 500ksps, Reference Mode 3, V
REF
= 4.096V; T
A
= T
MIN
to T
MAX
, unless
otherwise noted. Typical values are at T
A
= +25NC.) (Note 2)
PARAMETER
SCLK Period (CS Mode)
SYMBOL
t
SCLK
CONDITIONS
V
OVDD
> 4.5V
V
OVDD
> 2.7V
V
OVDD
> 2.3V
V
OVDD
> 4.5V
SCLK Period (Daisy-Chain Mode)
SCLK Low Time
SCLK High Time
SCLK Falling Edge to Data Valid
Delay
CNVST Low to DOUT D15 MSB
Valid (CS Mode)
CNVST High or Last SCLK Falling
Edge to DOUT High Impedance
DIN Valid Setup Time from SCLK
Falling Edge
DIN Valid Hold Time from SCLK
Falling Edge
SCLK Valid Setup Time to CNVST
Falling Edge
SCLK Valid Hold Time to CNVST
Falling Edge
t
SCLK
t
SCLKL
t
SCLKH
V
OVDD
> 4.5V
t
DDO
V
OVDD
> 2.7V
V
OVDD
> 2.3V
t
EN
t
DIS
V
OVDD
> 2.7V
V
OVDD
< 2.7V
CS
Mode
V
OVDD
> 4.5V
t
SDINSCK
V
OVDD
> 2.7V
V
OVDD
> 2.3V
t
HDINSCK
t
SSCKCNF
t
HSCKCNF
3
5
6
0
3
6
ns
ns
ns
ns
V
OVDD
> 2.7V
V
OVDD
> 2.3V
MIN
14
20
26
16
24
30
5
5
12
18
23
14
17
20
ns
ns
ns
ns
ns
ns
TYP
MAX
UNITS
ns
Note 2:
Maximum and minimum limits are fully production tested over specified supply voltage range and at a temperature of
+25°C. Limits over the operating temperature range are guaranteed by design and device characterization.
Note 3:
See the
Analog Inputs
and
Overvoltage Input Clamps
sections.
Note 4:
Static Performance limits are guaranteed by design and device characterization. For definitions, see the
Definitions
section.
Note 5:
Defined as the change in positive full-scale code transition caused by a
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