®
UC2842B/3B/4B/5B
UC3842B/3B/4B/5B
HIGH PERFORMANCE CURRENT MODE PWM CONTROLLER
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TRIMMED OSCILLATOR FOR PRECISE FRE-
QUENCY CONTROL
OSCILLATOR FREQUENCY GUARANTEED
AT 250kHz
CURRENT MODE OPERATION TO 500kHz
AUTOMATIC FEED FORWARD COMPENSA-
TION
LATCHING PWM FOR CYCLE-BY-CYCLE
CURRENT LIMITING
INTERNALLY TRIMMED REFERENCE WITH
UNDERVOLTAGE LOCKOUT
HIGH CURRENT TOTEM POLE OUTPUT
UNDERVOLTAGE LOCKOUT WITH HYSTER-
ESIS
LOW START-UP AND OPERATING CURRENT
Minidip
SO8
DESCRIPTION
The UC384xB family of control ICs provides the nec-
essary features to implement off-line or DC to DC
fixed frequency current mode control schemes with
a minimal external parts count. Internally imple-
mented circuits include a trimmed oscillator for pre-
cise DUTY CYCLE CONTROL under voltage lock-
out featuring start-up current less than 0.5mA, a pre-
cision reference trimmed for accuracy at the error
amp input, logic to insure latched operation, a PWM
comparator which also provides current limit control,
and a totem pole output stage designed to source
or sink high peak current. The output stage, suitable
for driving N-Channel MOSFETs, is low in the off-
state.
Differences between members of this family are the
under-voltage lockout thresholds and maximum duty
cycle ranges. The UC3842B and UC3844B have
UVLO thresholds of 16V (on) and 10V (off), ideally
suited off-line applications The corresponding thresh-
olds for the UC3843B and UC3845B are 8.5 V and 7.9
V. The UC3842B and UC3843B can operate to duty
cycles approaching 100%. A range of the zero to <
50 % is obtained by the UC3844B and UC3845B by
the addition of an internal toggle flip flop which blanks
the output off every other clock cycle.
BLOCK DIAGRAM
(toggle flip flop used only in UC3844B and UC3845B)
Vi
7
34V
GROUND
5
UVLO
S/R
5V
REF
INTERNAL
BIAS
VREF GOOD
LOGIC
RT/CT
4
OSC
ERROR AMP.
2R
R
1V
T
8
VREF
5V 50mA
2.50V
6
OUTPUT
VFB
COMP
CURRENT
SENSE
2
1
3
+
-
S
R
CURRENT
SENSE
COMPARATOR
PWM
LATCH
UC3842B
D95IN331
March 1999
1/15
UC2842B/3B/4B/5B - UC3842B/3B/4B/5B
ABSOLUTE MAXIMUM RATINGS
Symbol
V
i
V
i
I
O
E
O
Parameter
Supply Voltage (low impedance source)
Supply Voltage (Ii < 30mA)
Output Current
Output Energy (capacitive load)
Analog Inputs (pins 2, 3)
Error Amplifier Output Sink Current
P
tot
P
tot
T
stg
T
J
T
L
Power Dissipation at T
amb
≤
25
°C
(Minidip)
Power Dissipation at Tamb
≤
25
°C
(SO8)
Storage Temperature Range
Junction Operating Temperature
Lead Temperature (soldering 10s)
Value
30
Self Limiting
±1
5
– 0.3 to 5.5
10
1.25
800
– 65 to 150
– 40 to 150
300
A
µJ
V
mA
W
mW
°C
°C
°C
Unit
V
* All voltages are with respect to pin 5, all currents are positive into the specified terminal.
PIN CONNECTION
(top view)
Minidip/SO8
COMP
V
FB
I
SENSE
R
T
/C
T
1
2
3
4
D95IN332
8
7
6
5
V
REF
Vi
OUTPUT
GROUND
PIN FUNCTIONS
No
1
2
3
4
5
6
7
8
Function
COMP
V
FB
I
SENSE
R
T
/C
T
GROUND
OUTPUT
V
CC
V
ref
Description
This pin is the Error Amplifier output and is made available for loop compensation.
This is the inverting input of the Error Amplifier. It is normally connected to the switching
power supply output through a resistor divider.
A voltage proportional to inductor current is connected to this input. The PWM uses this
information to terminate the output switch conduction.
The oscillator frequency and maximum Output duty cycle are programmed by connecting
resistor R
T
to Vref and cpacitor C
T
to ground. Operation to 500kHz is possible.
This pin is the combined control circuitry and power ground.
This output directly drives the gate of a power MOSFET. Peak currents up to 1A are sourced
and sunk by this pin.
This pin is the positive supply of the control IC.
This is the reference output. It provides charging current for capacitor C
T
through resistor R
T
.
ORDERING NUMBERS
SO8
UC2842BD1;
UC2843BD1;
UC2844BD1;
UC2845BD1;
UC3842BD1
UC3843BD1
UC3844BD1
UC3845BD1
Minidip
UC2842BN;
UC2843BN;
UC2844BN;
UC2845BN;
UC3842BN
UC3843BN
UC3844BN
UC3845BN
2/15
UC2842B/3B/4B/5B - UC3842B/3B/4B/5B
THERMAL DATA
Symbol
R
th j-amb
Description
Thermal Resistance Junction-ambient.
max.
Minidip
100
SO8
150
Unit
°C/W
ELECTRICAL CHARACTERISTICS
( [note 1] Unless otherwise stated, these specifications apply for
-25 < T
amb
< 85°C for UC284XB; 0 < T
amb
< 70°C for UC384XB; V
i
= 15V (note 5); R
T
= 10K; C
T
= 3.3nF)
Symbol
Parameter
Test Conditions
UC284XB
UC384XB
Unit
Min. Typ. Max. Min. Typ. Max.
4.95 5.00 5.05 4.90 5.00 5.10
2
3
0.2
4.9
50
5
-30
49
T
j
= 25°C
48
T
A
= T
low
to T
high
225
T
J
= 25°C (R
T
= 6.2k, C
T
= 1nF)
–
–
–
7.8
7.5
T
A
= T
low
to T
high
(peak to peak)
25
-30
49
48
225
–
–
–
7.8
7.6
5.1
4.82
50
5
25
20
25
2
3
0.2
5.18
20
25
V
mV
mV
mV/°C
V
µV
mV
mA
KHz
KHz
KHz
%
%
V
mA
mA
V
µA
dB
MHz
dB
mA
mA
V
1.1
V
REFERENCE SECTION
V
REF
Output Voltage
∆V
REF
∆V
REF
Line Regulation
Load Regulation
T
j
= 25°C I
o
= 1mA
12V
≤
V
i
≤
25V
1
≤
I
o
≤
20mA
(Note 2)
Line, Load, Temperature
10Hz
≤
f
≤
10KHz T
j
= 25°C
(note 2)
T
amb
=
(note 2)
125°C,
1000Hrs
∆V
REF
/∆T Temperature Stability
Total Output Variation
e
N
Output Noise Voltage
Long Term Stability
I
SC
Output Short Circuit
-100 -180
52
–
250
0.2
1
1.6
8.3
–
55
56
275
1
–
–
8.8
8.8
-100 -180
52
–
250
0.2
0.5
1.6
8.3
–
55
56
275
1
–
–
8.8
8.8
OSCILLATOR SECTION
f
OSC
Frequency
∆f
OSC
/∆V
∆f
OSC
/∆T
V
OSC
I
dischg
Frequency Change with Volt. V
CC
= 12V to 25V
Frequency Change with Temp.
Oscillator Voltage Swing
Discharge Current (V
OSC
=2V) T
J
= 25°C
T
A
= T
low
to T
high
V
PIN1
= 2.5V
V
FB
= 5V
2V
≤
V
o
≤
4V
T
J
= 25°C
12V
≤
V
i
≤
25V
V
PIN2
= 2.7V V
PIN1
= 1.1V
V
PIN2
= 2.3V V
PIN1
= 5V
V
PIN2
= 2.3V;
R
L
= 15KΩ to Ground
V
PIN2
= 2.7V;
R
L
= 15KΩ to Pin 8
(note 3 & 4)
V
PIN1
= 5V (note 3)
12
≤
V
i
≤
25V (note 3)
ERROR AMP SECTION
V
2
Input Voltage
I
b
BW
PSRR
I
o
I
o
Input Bias Current
A
VOL
Unity Gain Bandwidth
Power Supply Rejec. Ratio
Output Sink Current
Output Source Current
V
OUT
High
V
OUT
Low
CURRENT SENSE SECTION
G
V
Gain
V
3
SVR
I
b
Maximum Input Signal
Supply Voltage Rejection
Input Bias Current
Delay to Output
2.45 2.50 2.55 2.42 2.50 2.58
-0.1
65
0.7
60
2
-0.5
5
90
1
70
12
-1
6.2
0.8
1.1
-1
65
0.7
60
2
-0.5
5
-0.1
90
1
70
12
-1
6.2
0.8
-2
2.85
0.9
3
1
70
-2
150
3.15 2.85
1.1
-10
300
0.9
3
1
70
-2
150
3.15
1.1
-10
300
V/V
V
dB
µA
ns
3/15
UC2842B/3B/4B/5B - UC3842B/3B/4B/5B
ELECTRICAL CHARACTERISTICS
(continued)
Symbol
OUTPUT SECTION
V
OL
V
OH
V
OLS
t
r
t
f
Output Low Level
I
SINK
= 20mA
I
SINK
= 200mA
Output High Level
I
SOURCE
= 20mA
I
SOURCE
= 200mA
UVLO Saturation
Rise Time
Fall Time
Start Threshold
VCC = 6V; I
SINK
= 1mA
T
j
= 25°C C
L
= 1nF (2)
T
j
= 25°C C
L
= 1nF (2)
X842B/4B
X843B/5B
Min Operating Voltage
After Turn-on
PWM SECTION
Maximum Duty Cycle
X842B/3B
X844B/5B
Minimum Duty Cycle
TOTAL STANDBY CURRENT
I
st
I
i
V
iz
Start-up Current
V
i
= 6.5V for UCX843B/45B
V
i
= 14V for UCX842B/44B
Operating Supply Current
Zener Voltage
V
PIN2
= V
PIN3
= 0V
I
i
= 25mA
30
0.3
0.3
12
36
0.5
0.5
17
30
0.3
0.3
12
36
0.5
0.5
17
mA
mA
mA
V
94
47
96
48
100
50
0
94
47
96
48
100
50
0
%
%
%
X842B/4B
X843B/5B
15
7.8
9
7.0
13
12
0.1
1.6
13.5
13.5
0.1
50
50
16
8.4
10
7.6
1.1
150
150
17
9.0
11
8.2
14.5
7.8
8.5
7.0
0.4
2.2
13
12
0.1
1.6
13.5
13.5
0.1
50
50
16
8.4
10
7.6
1.1
150
150
17.5
9.0
11.5
8.2
0.4
2.2
V
V
V
V
V
ns
ns
V
V
V
V
Parameter
Test Conditions
UC284XB
UC384XB
Unit
Min. Typ. Max. Min. Typ. Max.
UNDER-VOLTAGE LOCKOUT SECTION
Notes :
1. Max package power dissipation limits must be respected; low duty cycle pulse techniques are used during test maintain T
j
as
close to T
amb
as possible.
2. These parameters, although guaranteed, are not 100% tested in production.
3. Parameter measured at trip point of latch with V
PIN2
= 0.
4. Gain defined as :
∆
V
PIN1
A=
; 0
≤
V
PIN3
≤
0.8 V
∆
V
PIN3
5. Adjust V
i
above the start threshold before setting at 15 V.
4/15
UC2842B/3B/4B/5B - UC3842B/3B/4B/5B
Figure 1:
Open Loop Test Circuit.
V
REF
4.7KΩ
2N2222
100KΩ
ERROR AMP.
ADJUST
4.7KΩ
COMP
V
FB
1KΩ
I
SENSE
ADJUST
5KΩ
I
SENSE
R
T
/C
T
R
T
V
REF
1
2
8
7
V
i
0.1µF
OUTPUT
GROUND
1W
1KΩ
OUTPUT
A
0.1µF
V
i
UC2842B
3
4
6
5
C
T
D95IN343
GROUND
High peak currents associated with capacitive loads
necessitate careful grounding techniques. Timing
and bypass capacitors should be connected close
to pin 5 in a single point ground. The transistor and
5 KΩ potentiometer are used to sample the oscillator
waveform and apply an adjustable ramp to pin 3.
Figure 2:
Timing Resistor vs. Oscillator Fre-
quency
RT
(KΩ)
50
C
T
=
Figure 3:
Output Dead-Time vs. Oscillator Fre-
quency
D95IN334
D95IN333
%
20
0p
F
C
50
10
0p
F
T
=
C
20
T
=
50
C
T
=5nF
C
0p
30
20
C
T
=1nF
C
T
=500pF
C
T
=200pF
C
T
=2nF
C
T
=5nF
C
T
=10nF
F
T
=
1n
F
10
10
5
C
T
=2nF
C
T
=10nF
5
3
2
C
T
=100pF
2
V
i
=15V
T
A
=25˚C
1
0.8
10K
V
i
=15V
T
A
=25˚C
20K
30K
50K
100K
200K 300K
500K
f
OSC
(KHz)
1
10K
20K
30K
50K
100K
200K 300K
500K fOSC(KHz)
5/15
嵌入式系统
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