INTEGRATED CIRCUITS
74AVCM162835
18-bit registered driver with 15
Ω
termination resistors (3-State)
Product specification
File under Integrated Circuits ICL03
2001 Apr 20
Philips
Semiconductors
Philips Semiconductors
Product specification
18-bit registered driver with 15
Ω
termination resistors
(3-State)
74AVCM162835
FEATURES
•
Wide supply voltage range of 1.2 V to 3.6 V
•
Complies with JEDEC standard no. 8-1A/5/7.
•
CMOS low power consumption
•
Input/output tolerant up to 3.6 V
•
Low inductance multiple V
CC
and GND pins for minimum noise
and ground bounce
PIN CONFIGURATION
NC
NC
Y
0
GND
Y
1
Y
2
V
CC
Y
3
Y
4
Y
5
GND
Y
6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
GND
NC
A
0
GND
A
1
A
2
V
CC
A
3
A
4
A
5
GND
A
6
A
7
A
8
A
9
A
10
A
11
GND
A
12
A
13
A
14
V
CC
A
15
A
16
GND
A
17
CP
GND
•
Integrated 15
Ω
termination resistors to minimize output overshoot
and undershoot
•
Full PC133 solution provided when used with PCK2510S and
CBT16292
DESCRIPTION
The 74AVCM162835 is a 18-bit universal bus driver. Data flow is
controlled by output enable (OE), latch enable (LE) and clock inputs
(CP).
This product is designed to have an extremely fast propagation
delay and a minimum amount of power consumption.
To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pullup resistor (Live
Insertion).
Y
7
Y
8
Y
9
Y
10
Y
11
GND
Y
12
Y
13
Y
14
V
CC
Y
15
Y
16
GND
Y
17
OE
LE
SH00130
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
≤
2.0 ns; C
L
= 30 pF.
PARAMETER
SYMBOL
t
PHL
/t
PLH
Propagation delay
An to Yn
Propagation delay
LE to Yn;
CP to Yn
Input capacitance
Power dissipation capacitance per buffer
dissi ation ca acitance er
V
I
= GND to V
CC1
Outputs enabled
Output disabled
V
CC
= 1.8 V
V
CC
= 2.5 V
V
CC
= 3.3 V
V
CC
= 1.8 V
V
CC
= 2.5 V
V
CC
= 3.3 V
CONDITIONS
TYPICAL
2.6
2.0
1.7
2.8
2.2
1.8
5.0
25
6
UNIT
ns
t
PHL
/t
PLH
C
I
C
PD
ns
pF
pF
F
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+
S
(C
L
×
V
CC2
×
f
o
) where: f
i
= input frequency in MHz; C
L
= output load capacitance in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
S
(C
L
×
V
CC2
×
f
o
) = sum of outputs.
ORDERING INFORMATION
PACKAGES
56-Pin Plastic Thin Shrink Small Outline (TSSOP) Type II
TEMPERATURE
RANGE
–40 to +85
°C
ORDER CODE
74AVCM162835DGG
DRAWING
NUMBER
SOT364-1
2001 Apr 20
2
853-2170 26096
Philips Semiconductors
Product specification
18-bit registered driver with 15
Ω
termination
resistors (3-State)
74AVCM162835
PIN DESCRIPTION
PIN NUMBER
1, 2, 55
3, 5, 6, 8, 9, 10, 12, 13,
14, 15, 16, 17, 19, 20,
21, 23, 24, 26
4, 11, 18, 25, 32, 39, 46,
53, 56
7, 22, 35, 50
27
28
30
54, 52, 51, 49, 48, 47,
45, 44, 43, 42, 41, 40,
38, 37, 36, 34, 33, 31
SYMBOL
NC
Y
0
to Y
17
NAME AND FUNCTION
No connection
Data outputs
LOGIC SYMBOL (IEEE/IEC)
OE
CP
LE
27
30
28
C3
G2
EN1
2C3
GND
V
CC
OE
LE
CP
A
0
to A
17
Ground (0V)
Positive supply voltage
Output enable input
(active LOW)
Latch enable input
(active HIGH)
Clock input
Data inputs
Y
0
Y
1
Y
2
Y
3
Y
4
Y
5
Y
6
Y
7
Y
8
Y
9
Y
10
Y
11
3
5
6
8
9
10
12
13
14
15
16
17
19
20
21
23
24
26
1
∇
1
3D
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
A
17
LOGIC SYMBOL
Y
12
Y
13
Y
14
OE
Y
15
Y
16
CP
Y
17
SH00154
LE
A
0
FUNCTION TABLE
D
LE
CP
Y
0
INPUTS
OE
H
L
L
L
L
SH00138
LE
X
H
H
L
L
L
L
CP
X
X
X
↑
↑
H
L
A
X
L
H
L
H
X
X
OUTPUTS
Z
L
H
L
H
Y
01
Y
02
TO THE 17 OTHER CHANNELS
L
L
H
L
X
Z
↑
=
=
=
=
=
HIGH voltage level
LOW voltage level
Don’t care
High impedance “off” state
LOW-to-HIGH level transition
NOTES:
1. Output level before the indicated steady-state input conditions
were established, provided that CP is high before LE goes low.
2. Output level before the indicated steady-state input conditions
were established.
2001 Apr 20
3
Philips Semiconductors
Product specification
18-bit registered driver with 15
Ω
termination
resistors (3-State)
74AVCM162835
168-pin SDR SDRAM DIMM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
BACK SIDE
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
FRONT SIDE
74AVCM16835 74AVCM16835 74AVCM16835
PCK2509S or PCK2510S
The PLL clock distribution device and AVCM registered drivers reduce
signal loads on the memory controller and prevent timing delays and
waveform distortions that would cause unreliable operation
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
DC supply voltage
(according to JEDEC Low Voltage Standards)
V
CC
DC supply voltage
(for low voltage applications)
V
I
V
O
T
amb
t
r
, t
f
DC Input voltage range
DC output voltage range; output 3-State
DC output voltage range;
output HIGH or LOW state
Operating free-air temperature range
Input rise and fall times
V
CC
= 1.65 to 2.3 V
V
CC
= 2.3 to 3.0 V
V
CC
= 3.0 to 3.6 V
CONDITIONS
MIN
1.65
2.3
3.0
1.2
0
0
0
–40
0
0
0
MAX
1.95
2.7
3.6
3.6
3.6
3.6
V
V
CC
+85
30
20
10
°C
ns/V
V
UNIT
SDRAM
SW00408
V
2001 Apr 20
4
Philips Semiconductors
Product specification
18-bit registered driver with 15
Ω
termination
resistors (3-State)
74AVCM162835
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0 V)
SYMBOL
PARAMETER
V
CC
I
IK
V
I
I
OK
V
O
V
O
I
O
I
GND
, I
CC
T
stg
P
TOT
DC supply voltage
DC input diode current
DC input voltage
DC output diode current
DC output voltage; output 3-State
DC output voltage;
output HIGH or LOW state
DC output source or sink current
DC V
CC
or GND current
Storage temperature range
Power dissipation per package
–plastic thin-medium-shrink (TSSOP)
For temperature range: –40 to +125
°C
above +55
°C
derate linearly with 8 mW/K
V
I
t0
For all inputs
1
V
O
uV
CC
or V
O
t
0
Note 1
Note 1
V
O
= 0 to V
CC
CONDITIONS
RATING
–0.5 to +4.6
–50
–0.5 to 4.6
"50
–0.5 to 4.6
–0.5 to V
CC
+0.5
"50
"100
–65 to +150
600
UNIT
V
mA
V
mA
V
V
mA
mA
°C
mW
NOTE:
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions. Voltage are referenced to GND (ground = 0 V).
LIMITS
SYMBOL
PARAMETER
V
CC
= 1.2 V
V
IH
HIGH level Input voltage
In ut
V
CC
= 1.65 to 1.95 V
V
CC
= 2.3 to 2.7 V
V
CC
= 3.0 to 3.6 V
V
CC
= 1.2 V
V
IL
LOW level In ut voltage
Input
V
CC
= 1.65 to 1.95 V
V
CC
= 2.3 to 2.7 V
V
CC
= 3.0 to 3.6 V
V
CC
= 1.65 to 3.6 V; V
I
= V
IH
or V
IL
;
I
O
= –100
µA
V
OH
HIGH level output voltage
V
CC
= 1.65 V; V
I
= V
IH
or V
IL
; I
O
= –4 mA
V
CC
= 2.3 V; V
I
= V
IH
or V
IL
; I
O
= –8 mA
V
CC
= 3.0 V; V
I
= V
IH
or V
IL
; I
O
= –12 mA
V
CC
= 1.65 to 3.6 V; V
I
= V
IH
or V
IL
;
I
O
= 100
µA
V
OL
LOW level output voltage
V
CC
= 1.65 V; V
I
= V
IH
or V
IL
; I
O
= 4 mA
V
CC
= 2.3 V; V
I
= V
IH
or V
IL
; I
O
= 8 mA
V
CC
= 3.0 V; V
I
= V
IH
or V
IL
; I
O
= 12 mA
I
I
I
OFF
I
IHZ
/I
ILZ
I
OZ
Input leakage current
g
3-State output OFF-state current
3-State output OFF-state current
V
CC
= 1.65 to 3.6 V
1 65 3 6 V;
V
I
= V
CC
or GND
V
CC
= 0 V; V
I
or V
O
= 3.6 V
V
CC
= 1.65 to 3.6 V; V
I
= V
CC
or GND
V
CC
= 1.65 to 2.7 V; V
I
= V
IH
or V
IL
;
V
O
= V
CC
or GND
V
CC
= 3.0 to 3.6 V; V
I
= V
IH
or V
IL
;
V
O
= V
CC
or GND
V
CC
= 1.65 to 2.7 V; V
I
= V
CC
or GND; I
O
= 0
V
CC
= 3.0 to 3.6 V; V
I
= V
CC
or GND; I
O
= 0
TEST CONDITIONS
Temp = –40 to +85
°C
MIN
V
CC
0.65V
CC
1.7
2.0
–
–
–
–
V
CC
*0
20
*0.20
V
CC*
0.45
V
CC*
0.55
V
CC*
0.70
–
–
–
–
–
–
–
–
–
–
–
TYP
1
–
0.9
1.2
1.5
–
0.9
1.2
1.5
V
CC
V
CC*
0.10
V
CC*
0.28
V
CC*
0.32
GND
0.10
0.26
0.36
0.1
0.1
0.1
0.1
0.1
0.1
0.2
MAX
–
–
–
–
GND
0.35V
CC
0.7
0.8
–
–
–
–
0 20
0.20
0.45
0.55
0.70
2.5
"10
12.5
5
µA
10
20
40
µA
µ
µA
µA
µA
V
V
V
V
UNIT
3-State output OFF-state current
out ut
I
CC
Quiescent su ly current
supply
NOTES:
1. All typical values are at T
amb
= 25
°C.
2001 Apr 20
5
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