74LVT16244B; 74LVTH16244B
3.3 V 16-bit buffer/driver; 3-state
Rev. 11 — 1 March 2012
Product data sheet
1. General description
The 74LVT16244B; 74LVTH16244B is a high-performance BiCMOS product designed for
V
CC
operation at 3.3 V.
This device is a 16-bit buffer and line driver featuring non-inverting 3-state bus outputs.
The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer.
2. Features and benefits
16-bit bus interface
3-state buffers
Output capability: +64 mA and
32
mA
TTL input and output switching levels
Input and output interface capability to systems at 5 V supply
Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs
Power-up 3-state
Live insertion and extraction permitted
No bus current loading when output is tied to 5 V bus
Latch-up protection
JESD78B Class II exceeds 500 mA
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74LVT16244BDL
74LVTH16244BDL
74LVT16244BDGG
74LVTH16244BDGG
74LVT16244BEV
74LVT16244BBX
74LVTH16244BBX
40 C
to +85
C
40 C
to +125
C
VFBGA56
HXQFN60
40 C
to +85
C
TSSOP48
40 C
to +85
C
Name
SSOP48
Description
plastic shrink small outline package; 48 leads;
body width 7.5 mm
plastic thin shrink small outline package;
48 leads; body width 6.1 mm
plastic very thin fine-pitch ball grid array
package; 56 balls; body 4.5
7
0.65 mm
Version
SOT370-1
SOT362-1
SOT702-1
Type number
plastic compatible thermal enhanced extremely SOT1134-2
thin quad flat package; no leads; 60 terminals;
body 4
6
0.5 mm
Nexperia
74LVT16244B; 74LVTH16244B
3.3 V 16-bit buffer/driver; 3-state
4. Functional diagram
1
1OE
48
2OE
25
3OE
24
4OE
1A0
1A1
17
1A2
1A3
1
1OE
25
2Y0
3OE
2A0
2A1
41
40
2A0
8
9
30
29
4A0
4Y0
19
20
2A2
2A3
2A1
2Y1
4A1
4Y1
3A0
3A1
38
2A2
2Y2
11
27
4A2
4Y2
22
3A2
3A3
4A0
23
4A1
4A2
4A3
001aae506
47
46
1A0
1Y0
2
3
36
35
3A0
3Y0
13
14
1A1
1Y1
3A1
3Y1
EN1
EN2
EN3
EN4
1
1
2
3
5
6
1
2
8
9
11
12
1
3
13
14
16
17
1
4
19
20
22
23
1Y0
1Y1
1Y2
1Y3
2Y0
2Y1
2Y2
2Y3
3Y0
3Y1
3Y2
3Y3
4Y0
4Y1
4Y2
4Y3
44
1A2
1Y2
5
33
3A2
3Y2
16
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
43
1A3
1Y3
6
32
3A3
3Y3
37
2A3
2OE
2Y3
12
26
4A3
4OE
4Y3
48
24
001aae231
Pin numbers are shown for SSOP48 and TSSOP48
packages only.
Pin numbers are shown for SSOP48 and TSSOP48
packages only.
Fig 1. Logic symbol
Fig 2. IEC logic symbol
74LVT_LVTH16244B
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 11 — 1 March 2012
2 of 18
Nexperia
74LVT16244B; 74LVTH16244B
3.3 V 16-bit buffer/driver; 3-state
5. Pinning information
5.1 Pinning
74LVT16244B
74LVTH16244B
1OE
1Y0
1Y1
GND
1Y2
1Y3
V
CC
2Y0
2Y1
1
2
3
4
5
6
7
8
9
48 2OE
47 1A0
46 1A1
45 GND
44 1A2
43 1A3
42 V
CC
41 2A0
40 2A1
39 GND
38 2A2
37 2A3
36 3A0
35 3A1
34 GND
33 3A2
32 3A3
31 V
CC
30 4A0
29 4A1
28 GND
27 4A2
26 4A3
25 3OE
001aae507
GND 10
2Y2 11
2Y3 12
3Y0 13
3Y1 14
GND 15
3Y2 16
3Y3 17
V
CC
18
4Y0 19
4Y1 20
GND 21
4Y2 22
4Y3 23
4OE 24
74LVT16244B
ball A1
74LVTH16244B
index area
1 2 3 4 5 6
A
B
C
D
E
F
G
H
J
K
001aaj057
Transparent top view
Fig 3.
Pin configuration SOT370-1 (SSOP48) and
SOT362-1 (TSSOP48)
Fig 4.
Pin configuration SOT702-1 (VFBGA56)
74LVT_LVTH16244B
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 11 — 1 March 2012
3 of 18
Nexperia
74LVT16244B; 74LVTH16244B
3.3 V 16-bit buffer/driver; 3-state
terminal 1
index area
D1
A32
A31
A30
A29
A28
A27
D4
A1
D5
B20
B19
B18
D8
A26
A2
B1
A3
B2
A4
B3
A5
B4
A6
B5
A7
B6
A8
B7
A9
GND
(1)
B11
B12
B13
B15
B16
B17
A25
A24
A23
A22
74LVT16244B
74LVTH16244B
B14
A21
A20
A19
A18
A10
D6
B8
B9
B10
D7
A17
D2
A11
A12
A13
A14
A15
A16
D3
001aaj056
Transparent top view
(1) This is not a supply pin, the substrate is attached to this pad using conductive die attach material. There is no electrical or
mechanical requirement to solder this pad however if it is soldered the solder land should remain floating or be connected to
GND.
Fig 5.
Pin configuration SOT1134-2 (HXQFN60)
74LVT_LVTH16244B
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 11 — 1 March 2012
4 of 18
Nexperia
74LVT16244B; 74LVTH16244B
3.3 V 16-bit buffer/driver; 3-state
5.2 Pin description
Table 2.
Symbol
Pin description
Pin
SOT370-1 and
SOT362-1
1OE, 2OE,
3OE, 4OE
1, 48, 25, 24
SOT702-1
A1, A6, K6, K1
B2, B1, C2, C1
D2, D1, E2, E1
F1, F2, G1, G2
H1, H2, J1, J2
B3, B4, D3, D4, G3, G4,
J3, J4
C3, C4, H3, H4
B5, B6, C5, C6
D5, D6, E5, E6
F6, F5, G6, G5
H6, H5, J6, J5
A2, A3, A4, A5, K2, K3,
K4, K5
SOT1134-2
A30, A29, A14, A13
B20, A31, D5, D1
A2, B2, B3, A5
A6, B5, B6, A9
D2, D6, A12, B8
A32, A3, A8, A11, A16,
A19, A24, A27
A1, A10, A17, A26
B18, A28, D8, D4
A25, B16, B15, A22
A21, B13, B12, A18
D3, D7, A15, B10
A4, A7, A20, A23, B1,
B4, B7, B9, B11, B14,
B17, B19
output enable input (active LOW)
data output
data output
data output
data output
ground (0 V)
supply voltage
data input
data input
data input
data input
not connected
Description
1Y0 to 1Y3 2, 3, 5, 6
2Y0 to 2Y3 8, 9, 11, 12
3Y0 to 3Y3 13, 14, 16, 17
4Y0 to 4Y3 19, 20, 22, 23
GND
V
CC
4, 10, 15, 21, 28,
34, 39, 45
7, 18, 31, 42
1A0 to 1A3 47, 46, 44, 43
2A0 to 2A3 41, 40, 38, 37
3A0 to 3A3 36, 35, 33, 32
4A0 to 4A3 30, 29, 27, 26
n.c.
-
6. Functional description
Table 3.
Control
nOE
L
L
H
[1]
Function table
[1]
Input
nAn
L
H
X
Output
nYn
L
H
Z
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
V
O
I
IK
I
OK
Parameter
supply voltage
input voltage
output voltage
input clamping current
output clamping current
output in OFF-state or
HIGH-state
V
I
< 0 V
V
O
< 0 V
[1]
[1]
Conditions
Min
0.5
0.5
0.5
50
50
Max
+4.6
+7.0
+7.0
-
-
Unit
V
V
V
mA
mA
74LVT_LVTH16244B
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 11 — 1 March 2012
5 of 18
FPGA/CPLD
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