Data Sheet
FEATURES
+5 V to ±15 V operation
Unipolar or bipolar operation
True voltage output
Double-buffered inputs
Reset to minimum (DAC8413) or center scale (DAC8412)
Fast bus access time
Readback
Quad, 12-Bit DAC
Voltage Output with Readback
DAC8412/DAC8413
FUNCTIONAL BLOCK DIAGRAM
V
LOGIC
DATA
I/O
12
I/O
PORT
INPUT
REG A
INPUT
REG B
INPUT
REG C
INPUT
REG D
OUTPUT
REG A
OUTPUT
REG B
OUTPUT
REG C
OUTPUT
REG D
V
DD
V
REFH
DAC A
V
OUTA
DGND
A0
A1
R/W
CS
CONTROL
LOGIC
DAC B
V
OUTB
DAC C
V
OUTC
DAC D
APPLICATIONS
Automatic test equipment
Digitally controlled calibration
Servo controls
Process control equipment
V
OUTD
V
REFL
V
SS
Figure 1.
GENERAL DESCRIPTION
The DAC8412/DAC8413 are quad, 12-bit voltage output
DACs with readback capability. Built using a complementary
BiCMOS process, these monolithic DACs offer the user very
high package density.
Output voltage swing is set by the two reference inputs V
REFH
and V
REFL
. By setting the V
REFL
input to 0 V and V
REFH
to a
positive voltage, the DAC provides a unipolar positive output
range. A similar configuration with V
REFH
at 0 V and V
REFL
at a
negative voltage provides a unipolar negative output range.
Bipolar outputs are configured by connecting both V
REFH
and
V
REFL
to nonzero voltages. This method of setting output voltage
range has advantages over other bipolar offsetting methods
because it is not dependent on internal and external resistors
with different temperature coefficients.
Digital controls allow the user to load or read back data from any
DAC, load any DAC, and transfer data to all DACs at one time.
An active low RESET loads all DAC output registers to midscale
for the DAC8412 and zero scale for the DAC8413.
The DAC8412/DAC8413 are available in 28-lead plastic DIP,
28-lead ceramic DIP, 28-lead PLCC, and 28-lead LCC packages.
They can be operated from a wide variety of supply and reference
voltages with supplies ranging from single +5 V to ±15 V, and
references from +2.5 V to ±10 V. Power dissipation is less than
330 mW with ±15 V supplies and only 60 mW with a +5 V supply.
For MIL-STD-883 applications, contact your local Analog
Devices, Inc. sales office for the DAC8412/DAC8413/883 data
sheet, which specifies operation over the −55°C to +125°C
temperature range. All 883 parts are also available on Standard
Military Drawings 5962-91 76401MXA through 76404M3A.
0.500
0.375
+125°C
+25°C
LINEARITY ERROR (LSB)
0.250
0.125
0
–55°C
–0.125
–0.250
–0.375
–0.500
0
512
1024
1536
2046
2548
2560
DIGITAL INPUT CODE (Decimal)
3072
4096
V
DD
= +15V
V
SS
= –15V
V
REFH
= +10V
V
REFL
= –10V
T
A
= –55°C, +25°C, +125°C
00274-002
Figure 2. INL vs. Code Over Temperature
Rev. G
Document Feedback
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2000–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
00274-001
RESET
LDAC
DAC8412/DAC8413
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
aRevision History ............................................................................. 2
Specifications..................................................................................... 3
Electrical Characteristics ............................................................. 3
Absolute Maximum Ratings............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution .................................................................................. 7
Pin Configuration and Function Descriptions ............................. 8
Typical Performance Characteristics ............................................. 9
Theory of Operation ...................................................................... 14
Data Sheet
Introduction ................................................................................ 14
DACs ............................................................................................ 14
Glitch ............................................................................................ 14
Reference Inputs ......................................................................... 14
Digital I/O ................................................................................... 14
Coding ......................................................................................... 14
Supplies ........................................................................................ 15
Amplifiers .................................................................................... 15
Reference Configurations.......................................................... 16
Single +5 V Supply Operation .................................................. 17
Outline Dimensions ....................................................................... 18
Ordering Guide .......................................................................... 20
REVISION HISTORY
4/13—Rev. F to Rev. G
Changed Reference Low Input Current from 0 mA (min),
2 mA (typ), 2.75 mA (max) to −2.75 mA (min), −2 mA (typ),
0 mA (max); Table 1 ......................................................................... 3
Changes to Reference Configurations Section ........................... 17
9/09—Rev. E to Rev. F
Updated Figure Numbering .............................................. Universal
Removed Figure 7 ............................................................................. 6
Changes to Ordering Guide .......................................................... 20
6/07—Rev. D to Rev. E
Updated Format .................................................................. Universal
Added CERDIP Package .................................................... Universal
Changes to Specifications Section .................................................. 3
Changes to Absolute Maximum Ratings Section ......................... 7
Updated Outline Dimensions ....................................................... 18
Changes to Ordering Guide .......................................................... 20
3/00—Rev. C to Rev. D
Rev. G | Page 2 of 20
Data Sheet
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
DAC8412/DAC8413
V
DD
= +15.0 V, V
SS
= −15.0 V, V
LOGIC
= +5.0 V, V
REFH
= +10.0 V, V
REFL
= −10.0 V,−40°C ≤ T
A
≤ +85°C, unless otherwise noted.
1
Table 1.
Parameter
ACCURACY
Integral Nonlinearity Error
Differential Nonlinearity Error
Min-Scale Error
Full-Scale Error
Min-Scale Temperature Coefficient
Full-Scale Temperature Coefficient
Linearity Matching
REFERENCE
Positive Reference Input Voltage Range
2
Negative Reference Input Voltage Range
2
Reference High Input Current
Reference Low Input Current
Large Signal Bandwidth
AMPLIFIER CHARACTERISTICS
Output Current
Settling Time
Slew Rate
Analog Crosstalk
LOGIC CHARACTERISTICS
Logic Input High Voltage
Logic Input Low Voltage
Logic Output High Voltage
Logic Output Low Voltage
Logic Input Current
Input Capacitance
Digital Feedthrough
3
LOGIC TIMING CHARACTERISTICS
3, 4
Chip Select Write Pulse Width
Write Setup
Write Hold
Address Setup
Address Hold
Load Setup
Load Hold
Write Data Setup
Write Data Hold
Load Data Pulse Width
Reset Pulse Width
Chip Select Read Pulse Width
Read Data Hold
Read Data Setup
Data to High-Z
Chip Select to Data
Symbol
INL
DNL
V
ZSE
V
FSE
TCV
ZSE
TCV
FSE
Conditions
E grade
F grade
Monotonic over temperature
R
L
= 2 kΩ
R
L
= 2 kΩ
R
L
= 2 kΩ
R
L
= 2 kΩ
Adjacent DAC Matching
Min
Typ
±0.25
−1
±2
±2
15
20
±1
V
REFL
+ 2.5
−10
−2.75
−2.75
−3 dB, V
REFH
= 0 V to 10 V p-p
R
L
= 2 kΩ, C
L
= 100 pF
To 0.01%, 10 V step, R
L
= 1 kΩ
10% to 90%
–5
10
2.2
72
2.4
0.8
2.4
0.4
1
8
5
80
0
0
0
0
70
30
20
0
170
140
130
0
0
200
160
V
DD
− 2.5
V
REFH
− 2.5
+2.75
0
Max
±0.5
±1
Unit
LSB
LSB
LSB
LSB
LSB
ppm/°C
ppm/°C
LSB
V
V
mA
mA
kHz
mA
μs
V/μs
dB
V
V
V
V
μA
pF
nV-sec
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
I
REFH
I
REFL
BW
I
OUT
t
S
SR
+1.5
−2
160
+5
V
INH
V
INL
V
OH
V
OL
I
IN
C
IN
T
A
= 25°C
T
A
= 25°C
I
OH
= 0.4 mA
I
OL
= −1.6 mA
V
REFH
= 2.5 V, V
REFL
= 0 V
t
WCS
t
WS
t
WH
t
AS
t
AH
t
LS
t
LH
t
WDS
t
WDH
t
LDW
t
RESET
t
RCS
t
RDH
t
RDS
t
DZ
t
CSD
t
WCS
= 80 ns
t
WCS
= 80 ns
t
WCS
= 80 ns
t
WCS
= 80 ns
t
RCS
= 130 ns
t
RCS
= 130 ns
C
L
= 10 pF
C
L
= 100 pF
Rev. G | Page 3 of 20
DAC8412/DAC8413
Parameter
SUPPLY CHARACTERISTICS
Power Supply Sensitivity
Positive Supply Current
Negative Supply Current
Power Dissipation
1
2
Data Sheet
Symbol
PSS
I
DD
I
SS
P
DISS
Conditions
14.25 V ≤ V
DD
≤ 15.75 V
V
REFH
= 2.5 V
−10
Min
Typ
Max
150
12
330
Unit
ppm/V
mA
mA
mW
8.5
−6.5
All supplies can be varied ±5%, and operation is guaranteed. Device is tested with nominal supplies.
Operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed.
3
All parameters are guaranteed by design.
4
All input control signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
V
DD
= V
LOGIC
= +5.0 V ± 5%, V
SS
= 0.0 V, V
REFH
= +2.5 V, V
REFL
= 0.0 V, V
SS
= –5.0 V ± 5%, V
REFL
= −2.5 V, −40°C ≤ T
A
≤ +85°C,
unless otherwise noted.
1
Table 2.
Parameter
ACCURACY
Integral Nonlinearity Error
Symbol
INL
Conditions
E grade
F grade
V
SS
= 0.0 V, E grade
2
V
SS
= 0.0 V, F grade
2
Monotonic over temperature
V
SS
= −5.0 V
V
SS
= −5.0 V
V
SS
= 0.0 V
V
SS
= 0.0 V
Min
Typ
±0.5
Max
±1
±2
±2
±4
±4
±4
±8
±8
100
100
±1
V
REFL
+ 2.5
0
–2.5
–1.0
450
–1.25
7
2.2
2.4
0.8
2.4
0.45
1
8
150
0
0
0
0
70
50
+1.25
V
DD
− 2.5
V
REFH
− 2.5
V
REFH
− 2.5
+1.0
Units
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
ppm/°C
ppm/°C
LSB
V
V
V
mA
kHz
mA
μs
V/μs
V
V
V
V
μA
pF
ns
ns
ns
ns
ns
ns
ns
Differential Nonlinearity Error
Min-Scale Error
Full-Scale Error
Min-Scale Error
Full-Scale Error
Min-Scale Temperature Coefficient
Full-Scale Temperature Coefficient
Linearity Matching
REFERENCE
Positive Reference Input Voltage Range
3
Negative Reference Input Voltage Range
Reference High Input Current
Large Signal Bandwidth
AMPLIFIER CHARACTERISTICS
Output Current
Settling Time
Slew Rate
LOGIC CHARACTERISTICS
Logic Input High Voltage
Logic Input Low Voltage
Logic Output High Voltage
Logic Output Low Voltage
Logic Input Current
Input Capacitance
LOGIC TIMING CHARACTERISTICS
4, 5
Chip Select Write Pulse Width
Write Setup
Write Hold
Address Setup
Address Hold
Load Setup
Load Hold
DNL
V
ZSE
V
FSE
V
ZSE
V
FSE
TCV
ZSE
TCV
FSE
–1
Adjacent DAC matching
I
REFH
BW
I
OUT
t
S
SR
V
INH
V
INL
V
OH
V
OL
I
IN
C
IN
t
WCS
t
WS
t
WH
t
AS
t
AH
t
LS
t
LH
V
SS
= 0.0 V
V
SS
= −5.0 V
Code 0x000
−3 dB, V
REFH
= 0 V to 2.5 V p-p
R
L
= 2 kΩ, C
L
= 100 pF
To 0.01%, 2.5 V step, R
L
= 1 kΩ
10% to 90%
T
A
= 25°C
T
A
= 25°C
I
OH
= 0.4 mA
I
OL
= −1.6 mA
t
WCS
= 150 ns
t
WCS
= 150 ns
Rev. G | Page 4 of 20
Data Sheet
Parameter
Write Data Setup
Write Data Hold
Load Data Pulse Width
Reset Pulse Width
Chip Select Read Pulse Width
Read Data Hold
Read Data Setup
Data to High-Z
Chip Select to Data
SUPPLY CHARACTERISTICS
Power Supply Sensitivity
Positive Supply Current
Negative Supply Current
Power Dissipation
Symbol
t
WDS
t
WDH
t
LDW
t
RESET
t
RCS
t
RDH
t
RDS
t
DZ
t
CSD
PSS
I
DD
I
SS
P
DISS
Conditions
t
WCS
= 150 ns
t
WCS
= 150 ns
Min
20
0
180
150
170
20
0
DAC8412/DAC8413
Typ
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ppm/V
mA
mA
mW
mW
t
RCS
= 170 ns
t
RCS
= 170 ns
C
L
= 10 pF
C
L
= 100 pF
200
320
100
7
12
V
SS
= −5.0 V
V
SS
= 0 V
V
SS
= −5.0 V
−10
60
110
1
2
All supplies can be varied ±5%, and operation is guaranteed. Device is tested with V
DD
= 4.75 V.
For single-supply operation only (V
REFL
= 0.0 V, V
SS
= 0.0 V). Due to internal offset errors, INL and DNL are measured beginning at 0x005.
3
Operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed.
4
All parameters are guaranteed by design.
5
All input control signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
t
WCS
CS
t
WS
R/W
t
WH
t
AS
t
RDS
CS
t
AH
A0/A1
t
RCS
R/W
t
RDH
LDAC
t
LS
t
LH
t
LDW
t
AS
A0/A1
t
AH
DATA IN
t
WDS
t
DZ
RESET
t
WDH
t
CSD
Figure 3. Data Output (Read Timing)
Figure 4. Data Write (Input and Output Registers) Timing
Rev. G | Page 5 of 20
00274-004
DATA VALID
00274-003
DATA
OUT
HIGH-Z
HIGH-Z
t
RESET
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
