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Registered
Cyclone IV Device Handbook,
Volume 1
March 2016
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1–2
Chapter 1: Cyclone IV FPGA Device Family Overview
Cyclone IV Device Family Features
■
Cyclone IV GX devices offer up to eight high-speed transceivers that provide:
■
■
■
Data rates up to 3.125 Gbps
8B/10B encoder/decoder
8-bit or 10-bit physical media attachment (PMA) to physical coding sublayer
(PCS) interface
Byte serializer/deserializer (SERDES)
Word aligner
Rate matching FIFO
TX bit slipper for Common Public Radio Interface (CPRI)
Electrical idle
Dynamic channel reconfiguration allowing you to change data rates and
protocols on-the-fly
Static equalization and pre-emphasis for superior signal integrity
150 mW per channel power consumption
Flexible clocking structure to support multiple protocols in a single transceiver
block
■
■
■
■
■
■
■
■
■
■
Cyclone IV GX devices offer dedicated hard IP for PCI Express (PIPE) (PCIe)
Gen 1:
■
■
■
■
■
■
×1, ×2, and ×4 lane configurations
End-point and root-port configurations
Up to 256-byte payload
One virtual channel
2 KB retry buffer
4 KB receiver (Rx) buffer
■
Cyclone IV GX devices offer a wide range of protocol support:
■
■
■
■
■
■
■
■
■
■
■
PCIe (PIPE) Gen 1 ×1, ×2, and ×4 (2.5 Gbps)
Gigabit Ethernet (1.25 Gbps)
CPRI (up to 3.072 Gbps)
XAUI (3.125 Gbps)
Triple rate serial digital interface (SDI) (up to 2.97 Gbps)
Serial RapidIO (3.125 Gbps)
Basic mode (up to 3.125 Gbps)
V-by-One (up to 3.0 Gbps)
DisplayPort (2.7 Gbps)
Serial Advanced Technology Attachment (SATA) (up to 3.0 Gbps)
OBSAI (up to 3.072 Gbps)
Cyclone IV Device Handbook,
Volume 1
March 2016 Altera Corporation
Chapter 1: Cyclone IV FPGA Device Family Overview
Device Resources
1–3
■
Up to 532 user I/Os
■
■
■
LVDS interfaces up to 840 Mbps transmitter (Tx), 875 Mbps Rx
Support for DDR2 SDRAM interfaces up to 200 MHz
Support for QDRII SRAM and DDR SDRAM up to 167 MHz
■
■
Up to eight phase-locked loops (PLLs) per device
Offered in commercial and industrial temperature grades
Device Resources
Table 1–1
lists Cyclone IV E device resources.
Table 1–1. Resources for the Cyclone IV E Device Family
EP4CE115
114,480
3,888
266
4
20
8
528
EP4CE10
EP4CE15
EP4CE22
EP4CE30
EP4CE40
EP4CE55
EP4CE75
75,408
2,745
200
4
20
8
426
EP4CE6
6,272
270
15
2
10
8
(1)
Resources
Logic elements (LEs)
Embedded memory
(Kbits)
Embedded 18 × 18
multipliers
General-purpose PLLs
Global Clock Networks
User I/O Banks
Maximum user I/O
Note to
Table 1–1:
10,320
414
23
2
10
8
179
15,408
504
56
4
20
8
343
22,320
594
66
4
20
8
153
28,848
594
66
4
20
8
532
39,600
1,134
116
4
20
8
532
55,856
2,340
154
4
20
8
374
179
(1) The user I/Os count from pin-out files includes all general purpose I/O, dedicated clock pins, and dual purpose configuration pins. Transceiver
pins and dedicated configuration pins are not included in the pin count.
March 2016
Altera Corporation
Cyclone IV Device Handbook,
Volume 1
1–4
Chapter 1: Cyclone IV FPGA Device Family Overview
Device Resources
Table 1–2
lists Cyclone IV GX device resources.
Table 1–2. Resources for the Cyclone IV GX Device Family
EP4CGX110
EP4CGX150
4
4
11
EP4CGX15
EP4CGX22
EP4CGX30
EP4CGX30
EP4CGX50
EP4CGX75
(1)
(2)
(3)
(3)
(3)
Resources
Logic elements (LEs)
Embedded memory (Kbits)
Embedded 18 × 18 multipliers
General purpose PLLs
Multipurpose PLLs
Global clock networks
High-speed transceivers
(6)
14,400
540
0
1
2
(5)
21,280
756
40
2
2
(5)
29,440
1,080
80
2
2
(5)
29,440
1,080
80
4
2
(4)
(5)
49,888
2,502
140
4
4
(4)
(5)
73,920
4,158
198
4
4
(4)
(5)
109,424
5,490
280
4
4
(4)
(5)
149,760
6,480
360
(4)
(5)
20
2
2.5
1
9
(7)
20
4
2.5
1
9
(7)
20
4
2.5
1
9
(7)
30
4
3.125
1
11
(8)
30
8
3.125
1
11
(8)
30
8
3.125
1
11
(8)
30
8
3.125
1
11
(8)
30
8
3.125
1
(8)
Transceiver maximum data rate
(Gbps)
PCIe (PIPE) hard IP blocks
User I/O banks
Maximum user I/O
Notes to
Table 1–2:
(9)
72
150
150
290
310
310
475
475
(1) Applicable for the F169 and F324 packages.
(2) Applicable for the F484 package.
(3) Only two multipurpose PLLs for F484 package.
(4) Two of the general purpose PLLs are able to support transceiver clocking. For more information, refer to the
Clock Networks and PLLs in
Cyclone IV Devices
chapter.
(5) You can use the multipurpose PLLs for general purpose clocking when they are not used to clock the transceivers. For more information, refer
to the
Clock Networks and PLLs in Cyclone IV Devices
chapter.
(6) If PCIe
1,
you can use the remaining transceivers in a quad for other protocols at the same or different data rates.
(7) Including one configuration I/O bank and two dedicated clock input I/O banks for HSSI reference clock input.
(8) Including one configuration I/O bank and four dedicated clock input I/O banks for HSSI reference clock input.
(9) The user I/Os count from pin-out files includes all general purpose I/O, dedicated clock pins, and dual purpose configuration pins. Transceiver
pins and dedicated configuration pins are not included in the pin count.
Cyclone IV Device Handbook,
Volume 1
March 2016 Altera Corporation
(3)
Package Matrix
Table 1–3
lists Cyclone IV E device package offerings.
Table 1–3. Package Offerings for the Cyclone IV E Device Family
(1),
Package
Size (mm)
Pitch (mm)
User I/O
Device
EP4CE6
EP4CE10
EP4CE15
EP4CE22
EP4CE30
EP4CE40
EP4CE55
EP4CE75
EP4CE115
E144
22 × 22
0.5
User I/O
(3)
(2)
Chapter 1: Cyclone IV FPGA Device Family Overview
Package Matrix
User I/O
User I/O
User I/O
User I/O
User I/O
User I/O
User I/O
—
—
—
—
532
532
374
426
528
(3)
(3)
(3)
(3)
(3)
(3)
(3)
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
91
91
81
79
—
—
—
—
—
21
21
18
17
—
—
—
—
—
—
—
89
—
—
—
—
—
—
—
—
21
—
—
—
—
—
—
—
—
165
—
—
—
—
—
—
—
—
53
—
—
—
—
—
—
179
179
165
153
—
—
—
—
—
66
66
53
52
—
—
—
—
—
179
179
165
153
—
—
—
—
—
66
66
53
52
—
—
—
—
—
—
—
—
—
193
193
—
—
—
—
—
—
—
68
68
—
—
—
—
—
—
—
—
328
324
292
—
—
—
—
—
—
124
132
110
—
—
—
343
—
328
328
324
292
280
—
—
137
—
124
124
132
110
103
—
—
—
—
224
224
160
178
230
Notes to
Table 1–3:
(1) The E144 package has an exposed pad at the bottom of the package. This exposed pad is a ground pad that must be connected to the ground plane of your PCB. Use this exposed pad for electrical
connectivity and not for thermal purposes.
(2) Use the Pin Migration View window in Pin Planner of the Quartus II software to verify the pin migration compatibility when you perform device migration. For more information, refer to the
I/O
Management
chapter in volume 2 of the
Quartus II Handbook.
(3) This includes both dedicated and emulated LVDS pairs. For more information, refer to the
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