19-2383; Rev 1; 11/03
1:2 Differential PECL/ECL/LVPECL/LVECL
Clock and Data Driver
General Description
The MAX9320B low-skew, 1-to-2 differential driver is
designed for clock and data distribution. The input is
reproduced at two differential outputs. The differential
input can be adapted to accept single-ended inputs by
applying an external reference voltage.
The MAX9320B features ultra-low propagation delay
(208ps), part-to-part skew (20ps), and output-to-output
skew (6ps) with 30mA maximum supply current, mak-
ing this device ideal for clock distribution. For interfac-
ing to differential PECL and LVPECL signals, this
device operates over a +3.0V to +5.5V supply range,
allowing high-performance clock or data distribution in
systems with a nominal 3.3V or 5V supply. For differen-
tial ECL and LVECL operation, this device operates
from a -3.0V to -5.5V supply.
The MAX9320B is offered in industry-standard 8-pin
TSSOP and SO packages.
Features
o
Improved Second Source of the MC10EP11D
o
+3.0V to +5.5V Differential PECL/LVPECL
Operation
o
-3.0V to -5.5V ECL/LVECL Operation
o
Low 22mA Supply Current
o
20ps Part-to-Part Skew
o
6ps Output-to-Output Skew
o
208ps Propagation Delay
o
Minimum 300mV Output at 3GHz
o
Outputs Low for Open Input
o
ESD Protection >2kV (Human Body Model)
MAX9320B
Applications
Precision Clock Distribution
Low-Jitter Data Repeater
Protection Switching
PART
MAX9320BESA
MAX9320BEUA
Ordering Information
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
8 SO
8 TSSOP
Pin Configuration
D
V
IHD
- V
ILD
D
t
PLHD
Q_
V
OH
- V
OL
Q
t
PHLD
V
IHD
V
ILD
Q0 1
V
OH
V
OL
MAX9320B
50kΩ
80kΩ
8 V
CC
7 D
60kΩ
6 D
Q0 2
Q1 3
80%
0V (DIFFERENTIAL)
(Q_) - (Q_)
20%
t
R
80%
0V (DIFFERENTIAL)
20%
t
F
100kΩ
Q1 4
5 V
EE
TSSOP/SO
Figure 1. Differential Transition Time and Propagation Delay
Timing Diagram
________________________________________________________________
Maxim Integrated Products
1
For pricing delivery, and ordering information please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1:2 Differential PECL/ECL/LVPECL/LVECL
Clock and Data Driver
MAX9320B
ABSOLUTE MAXIMUM RATINGS
V
CC
to V
EE
.............................................................................+6V
D or
D....................................................V
EE
- 0.3V to V
CC
+ 0.3V
D or
D
with the Other Floating............. V
CC
- 5.0V to V
CC
+ 0.3V
D to
D
.................................................................................±3.0V
Continuous Output Current .................................................50mA
Surge Output Current........................................................100mA
Continuous Output Power Dissipation (TA = +70°C)
8-Pin TSSOP
(derate 4.5mW/°C above +70°C) .................................362mW
8-Pin SO
(derate 5.9mW/°C above +70°C) .................................471mW
Junction-to-Ambient Thermal Resistance in Still Air
8-Pin TSSOP ............................................................+221°C/W
8-Pin SO...................................................................+170°C/W
Junction-to-Ambient Thermal Resistance with 500
LFPM Airflow
8-Pin TSSOP ............................................................+155°C/W
8-Pin SO.....................................................................+99°C/W
Junction-to-Case Thermal Resistance
8-Pin TSSOP ..............................................................+39°C/W
8-Pin SO.....................................................................+40°C/W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
ESD Protection
Human Body Model (D,
D,
Q_,
Q_)
.................................>2kV
Soldering Temperature (10s) ...........................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
CC
- V
EE
= 3.0V to 5.5V, outputs loaded with 50Ω ±1% to V
CC
- 2V. Typical values are at V
CC
- V
EE
= 5.0V, V
IHD
= V
CC
- 1.0V, V
ILD
= V
CC
- 1.5V, unless otherwise noted.) (Notes 1, 2, 3)
PARAMETER
SYMBOL
CONDITIONS
-40°C
MIN
TYP
MAX
MIN
+25°C
TYP
MAX
MIN
+85°C
TYP
MAX
UNITS
DIFFERENTIAL INPUT (D,
D)
High Voltage of
Differential
Input
Low Voltage of
Differential
Input
Differential
Input Voltage
Input High
Current
D Input Low
Current
D
Input Low
Current
Single-Ended
Output High
Voltage
V
IHD
V
EE
+ 1.2
V
CC
V
EE
+ 1.2
V
CC
V
EE
+ 1.2
V
CC
V
V
ILD
V
IHD
-
V
ILD
I
IH
I
ILD
I
ILD
V
CC
- V
EE
≤
3.8V
V
CC
- V
EE
≥
3.8V
V
CC
- V
EE
≤
3.8V
V
CC
- V
EE
≥
3.8V
V
EE
V
CC
- 0.1
3.0
150
V
EE
V
CC
- 0.1
3.0
150
V
EE
V
CC
- 0.1
3.0
150
V
0.1
0.1
0.1
V
µA
µA
µA
-100
-140
-150
-175
+100
+140
+150
+175
-100
-140
-150
-175
+100
+140
+150
+175
-100
-140
-150
-175
+100
+140
+150
+175
DIFFERENTIAL OUTPUTS (Q_,
Q__
)
V
OH
Figure 1
V
CC
- 1.135
V
CC
- 0.885
V
CC
- 1.07
V
CC
- 0.82
V
CC
- 1.01
V
CC
- 0.76
V
2
_______________________________________________________________________________________
1:2 Differential PECL/ECL/LVPECL/LVECL
Clock and Data Driver
DC ELECTRICAL CHARACTERISTICS (continued)
(V
CC
- V
EE
= 3.0V to 5.5V, outputs loaded with 50Ω ±1% to V
CC
- 2V. Typical values are at V
CC
- V
EE
= 5.0V, V
IHD
= V
CC
- 1.0V, V
ILD
= V
CC
- 1.5V, unless otherwise noted.) (Notes 1, 2, 3)
PARAMETER
Single-Ended
Output Low
Voltage
Differential
Output Voltage
POWER SUPPLY
Supply Current
I
EE
(Note 4)
20
28
22
28
23
30
mA
SYMBOL
CONDITIONS
-40°C
MIN
V
CC
- 1.935
550
TYP
MAX
MIN
+25°C
TYP
MAX
V
CC
- 1.62
MIN
V
CC
- 1.81
550
+85°C
TYP
MAX
V
CC
- 1.56
UNITS
MAX9320B
V
OL
V
OH
- V
OL
Figure 1
V
CC
V
CC
- 1.685 - 1.87
550
V
Figure 1
mV
AC ELECTRICAL CHARACTERISTICS
(V
CC
- V
EE
= 3.0V to 5.5V, outputs loaded with 50Ω ±1% to V
CC
- 2V, input frequency
≤
1.5GHz, input transition time = 125ps (20% to
80%), V
IHD
= V
EE
+ 1.2V to V
CC
, V
ILD
= V
EE
to V
CC
- 0.15V, V
IHD
- V
ILD
= 0.15V to 3.0V. Typical values are at V
CC
- V
EE
= 5.0V, V
IHD
= V
CC
- 1V, V
ILD
= V
CC
- 1.5V, unless otherwise noted.) (Note 5)
PARAMETER
Differential
Input-to-
Output Delay
Output-to-
Output Skew
Part-to-Part
Skew
SYMBOL
t
PLHD
,
t
PHLD
CONDITIONS
-40°C
MIN
145
TYP
220
MAX
265
MIN
155
+25°C
TYP
208
MAX
265
MIN
160
+85°C
TYP
203
MAX
270
UNITS
Figure 1
ps
t
SKOO
(Note 6)
6
30
6
30
6
30
ps
t
SKPP
(Note 7)
f
IN
= 1.5GHz, clock
pattern (Note 8)
20
1.7
0.6
120
2.8
1.5
20
1.7
0.6
110
2.8
1.5
20
1.7
0.6
110
2.8
ps
Added
Random Jitter
t
RJ
f
IN
= 3.0GHz, clock
pattern (Note 8)
3.0Gbps
2
23
- 1 PRBS pattern
(Note 8)
ps
(RMS)
1.5
ps
(
P-P
)
Added
Deterministic
Jitter
t
DJ
57
80
57
80
57
80
_______________________________________________________________________________________
3
1:2 Differential PECL/ECL/LVPECL/LVECL
Clock and Data Driver
MAX9320B
AC ELECTRICAL CHARACTERISTICS (continued)
(V
CC
- V
EE
= 3.0V to 5.5V, outputs loaded with 50Ω ±1% to V
CC
- 2V, input frequency
≤
1.5GHz, input transition time = 125ps (20% to
80%), V
IHD
= V
EE
+ 1.2V to V
CC
, V
ILD
= V
EE
to V
CC
- 0.15V, V
IHD
- V
ILD
= 0.15V to 3.0V. Typical values are at V
CC
- V
EE
= 5.0V, V
IHD
= V
CC
- 1V, V
ILD
= V
CC
- 1.5V, unless otherwise noted.) (Note 5)
PARAMETER
SYMBOL
CONDITIONS
V
OH
- V
OL
≥
300mV,
clock pattern,
Figure 1
f
MAX
V
OH
- V
OL
≥
550mV,
clock pattern,
Figure 1
-40°C
MIN
3.0
TYP
MAX
MIN
3.0
+25°C
TYP
MAX
MIN
3.0
GHz
2.0
2.0
2.0
+85°C
TYP
MAX
UNITS
Switching
Frequency
Output
Rise/Fall Time
(20% to 80%)
t
R
, t
F
Figure 1
50
95
120
50
98
120
50
105
120
ps
Note 1:
Measurements are made with the device in thermal equilibrium.
Note 2:
Current into a pin is defined as positive. Current out of a pin is defined as negative.
Note 3:
DC parameters production tested at T
A
= +25°C. Guaranteed by design and characterization over the full operating temper-
ature range.
Note 4:
All pins open except V
CC
and V
EE
.
Note 5:
Guaranteed by design and characterization. Limits are set at ±6 sigma.
Note 6:
Measured between outputs of the same part at the signal crossing points for a same-edge transition.
Note 7:
Measured between outputs of different parts at the signal crossing points under identical conditions for a same-edge transition.
Note 8:
Device jitter added to the input signal.
Typical Operating Characteristics
(V
CC
= 5V, V
EE
= 0, input transition time = 125ps (20% to 80%), V
IHD
= V
CC
- 1V, V
ILD
= V
CC
- 1.5V, f
IN
= 1.5GHz, outputs loaded with
50Ω to V
CC
- 2V, T
A
= +25°C, unless otherwise noted.)
SUPPLY CURRENT, I
EE
vs. TEMPERATURE
24
23
SUPPLY CURRENT (mA)
22
21
20
19
18
17
16
15
-40
-15
10
35
60
85
TEMPERATURE (°C)
MAX9320B toc01
OUTPUT AMPLITUDE, V
OH
- V
OL
vs. FREQUENCY
0.7
OUTPUT AMPLITUDE (V)
0.6
0.5
0.4
0.3
0.2
0.1
0
0
500
1000 1500 2000 2500 3000 3500
FREQUENCY (MHz)
85
80
MAX9320B toc02
TRANSITION TIME vs. TEMPERATURE
MAX9320B toc03
25
0.8
110
105
TRANSITION TIME (ps)
100
95
90
t
F
t
R
-40
-15
10
35
60
85
TEMPERATURE (°C)
4
_______________________________________________________________________________________
1:2 Differential PECL/ECL/LVPECL/LVECL
Clock and Data Driver
Typical Operating Characteristics (continued)
(V
CC
= 5V, V
EE
= 0, input transition time = 125ps (20% to 80%), V
IHD
= V
CC
- 1V, V
ILD
= V
CC
- 1.5V, f
IN
= 1.5GHz, outputs loaded with
50Ω to V
CC
- 2V, T
A
= +25°C, unless otherwise noted.)
PROPAGATION DELAY vs. HIGH VOLTAGE
OF DIFFERENTIAL INPUT, V
IHD
V
IHD
- V
ILD
= 0.5V
215
PROPAGATION DELAY (ps)
210
205
200
195
190
1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8 5.2 5.6
V
IHD
(V)
t
PHLD
t
PLHD
MAX9320B toc04
MAX9320B
PROPAGATION DELAY vs. TEMPERATURE
230
PROPAGATION DELAY (ps)
220
210
200
190
180
170
160
-40
-15
10
35
60
85
TEMPERATURE (°C)
t
PHLD
MAX9320B toc05
220
240
t
PLHD
Pin Description
PIN
1
2
3
4
5
6
7
8
NAME
Q0
Q0
Q1
Q1
V
EE
D
D
V
CC
FUNCTION
Noninverting Q0 Output. Typically terminate with 50Ω resistor to V
CC
- 2V.
Inverting Q0 Output. Typically terminate with 50Ω resistor to V
CC
- 2V.
Noninverting Q1 Output. Typically terminate with 50Ω resistor to V
CC
- 2V.
Inverting Q1 Output. Typically terminate with 50Ω resistor to V
CC
- 2V.
Negative Supply Voltage
Inverting Differential Input. 50kΩ pullup to V
CC
and 100kΩ pulldown to V
EE
.
Noninverting Differential Input. 80kΩ pullup to V
CC
and 60kΩ pulldown to V
EE
.
Positive Supply Voltage. Bypass from V
CC
to V
EE
with 0.1µF and 0.01µF ceramic capacitors. Place the
capacitors as close to the device as possible with the smaller value capacitor closest to the device.
_______________________________________________________________________________________
5
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