SA571
Compandor
The SA571 is a versatile low cost dual gain control circuit in which
either channel may be used as a dynamic range compressor or
expandor. Each channel has a full−wave rectifier to detect the average
value of the signal, a linerarized temperature−compensated variable
gain cell, and an operational amplifier.
The SA571 is well suited for use in cellular radio and radio
communications systems, modems, telephone, and satellite
broadcast/receive audio systems.
Features
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MARKING
DIAGRAMS
16
16
1
SOIC−16 WB
D SUFFIX
CASE 751G
SA571D
AWLYYWWG
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Complete Compressor and Expandor in one IChip
Temperature Compensated
Greater than 110 dB Dynamic Range
Operates Down to 6.0 VDC
System Levels Adjustable with External Components
Distortion may be Trimmed Out
Dynamic Noise Reduction Systems
Voltage Controlled Amplifier
Pb−Free Packages are Available*
1
16
16
1
PDIP−16
N SUFFIX
CASE 648
A
WL
YY
WW
G
1
SA571N
AWLYYWWG
Applications
Cellular Radio
High Level Limiter
Low Level Expandor − Noise Gate
Dynamic Filters
CD Player
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
PIN CONNECTIONS
D, and N Packages*
RECT CAP 1
RECT IN 1
DG
CELL IN 1
GND
INV. IN 1
RES. R
3
1
OUTPUT 1
THD TRIM 1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
RECT CAP 2
RECT IN 2
DG
CELL IN 2
V
CC
INV. IN 2
RES. R
3
2
OUTPUT 2
THD TRIM 2
TOP VIEW
*SOL − Released in Large SO Package Only.
ORDERING INFORMATION
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
©
Semiconductor Components Industries, LLC, 2006
1
March, 2006 − Rev. 4
Publication Order Number:
SA571/D
SA571
THD TRIM
R
3
INVERTER IN
R
3
20kW
VARIABLE
GAIN
V
REF
RECT IN R
1
10kW
RECTIFIER
RECT CAP
R
4
30kW
1.8V
−
OUTPUT
+
DG IN
R
2
20kW
Figure 1. Block Diagram
MAXIMUM RATINGS
Rating
Maximum Operating Voltage
Operating Ambient Temperature Range
Operating Junction Temperature
Power Dissipation
Thermal Resistance, Junction−to−Ambient
N Package
D Package
Symbol
V
CC
T
A
T
J
P
D
R
qJA
Value
18
−40 to +85
150
400
75
105
Unit
VDC
°C
°C
mW
°C/W
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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2
SA571
ELECTRICAL CHARACTERISTICS
(V
CC
= +15 V, T
A
= 25°C, unless otherwise noted)
Characteristic
Supply Voltage
Supply Current
Output Current Capability
Output Slew Rate
Gain Cell Distortion (Note 2)
Resistor Tolerance
Internal Reference Voltage
Output DC Shift (Note 3)
Expandor Output Noise
Unity Gain Level (Note 5)
Gain Change (Notes 2 and 4)
Reference Drift (Note 4)
Resistor Drift (Note 4)
Tracking Error
(Measured Relative to Value at Unity Gain)
Equals [V
O
− V
O
(unity gain)] dB − V
2
dBm
Channel Separation
1.
2.
3.
4.
5.
Input to V
1
and V
2
grounded.
Measured at 0 dBm, 1.0 kHz.
Expandor AC input change from no signal to 0 dBm.
Relative to value at T
A
= 25°C.
0 dBm = 775 mV
RMS
.
Symbol
V
CC
I
CC
I
OUT
SR
Test Conditions
−
No Signal
−
−
Untrimmed
Trimmed
−
−
Untrimmed
No Signal, 15 Hz−20 kHz
(Note 1)
1.0 kHz
−
−
−40°C to +85°C
Rectifier Input,
V
CC
= +6.0 V
V
2
= +6.0 dBm, V
1
= 0 dB
V
2
= −30 dBm, V
1
= 0 dB
−
Min
6.0
−
±
20
−
−
−
1.65
−
−
−1.5
−
−
−
−
+0.2
+0.2
−
60
−1.0, +1.5
−
dB
Typ
−
4.2
−
±
.5
0.5
0.1
±
5
1.8
±
90
20
0
±
0.1
+2.0, −25
+10, −12
Max
18
4.8
−
−
2.0
±
15
1.95
±
150
60
+1.5
−
+20, −50
−
Unit
V
mA
mA
V/ms
%
%
V
mV
mV
dBm
dB
mV
%
dB
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SA571
Circuit Description
COMPRESSOR INPUT LEVEL OR EXPANDOR
OUTPUT LEVEL (dBm)
The SA571 compandor building blocks, as shown in the
block diagram, are a full−wave rectifier, a variable gain cell,
an operational amplifier and a bias system. The arrangement
of these blocks in the IC result in a circuit which can perform
well with few external components, yet can be adapted to
many diverse applications.
The full−wave rectifier rectifies the input current which
flows from the rectifier input, to an internal summing node
which is biased at V
REF
. The rectified current is averaged on
an external filter capacitor tied to the C
RECT
terminal, and
the average value of the input current controls the gain of the
variable gain cell. The gain will thus be proportional to the
average value of the input signal for capacitively−coupled
voltage inputs as shown in the following equation. Note that
for capacitively−coupled inputs there is no offset voltage
capable of producing a gain error. The only error will come
from the bias current of the rectifier (supplied internally)
which is less than 0.1
mA.
G
T
|V
IN
*
V
REF
| avg
R
1
or
as brought out externally. A resistor, R
3
, is brought out from
the summing node and allows compressor or expander gain
to be determined only by internal components.
The output stage is capable of
±
20 mA output current.
This allows a +13 dBm (3.5 V
RMS
) output into a 300
W
load
which, with a series resistor and proper transformer, can
result in +13 dBm with a 600
W
output impedance.
A bandgap reference provides the reference voltage for all
summing nodes, a regulated supply voltage for the rectifier
and
DG
cell, and a bias current for the
DG
cell. The low
tempco of this type of reference provides very stable biasing
over a wide temperature range.
The typical performance characteristics illustration
shows the basic input−output transfer curve for basic
compressor or expander circuits.
+20
+10
0
−10
−20
−30
−40
−50
−60
−70
−80
−40
−30 −20 −10
0
+10
G
T
| V
IN
| avg
R
1
The speed with which gain changes to follow changes in
input signal levels is determined by the rectifier filter
capacitor. A small capacitor will yield rapid response but
will not fully filter low frequency signals. Any ripple on the
gain control signal will modulate the signal passing through
the variable gain cell. In an expander or compressor
application, this would lead to third harmonic distortion, so
there is a trade−off to be made between fast attack and decay
times and distortion. For step changes in amplitude, the
change in gain with time is shown by this equation.
G(t)
+
(G
initial
*
G
final
) e
t
+
10kW
C
RECT
*t
t
COMPRESSOR OUTPUT LEVEL
OR
EXPANDOR INPUT LEVEL (dBm)
Figure 2. Basic Input−Output Transfer Curve
)
G
final
V
CC
= 15V
0.1mF
13
6, 11
20kW
2.2mF 20kW
V
1
3, 14
DG
−
+
10mF
The variable gain cell is a current−in, current−out device
with the ratio I
OUT
/I
IN
controlled by the rectifier. I
IN
is the
current which flows from the
DG
input to an internal
summing node biased at V
REF
. The following equation
applies for capacitively−coupled inputs. The output current,
I
OUT
, is fed to the summing node of the op amp.
I
IN
+
V
IN
*
V
REF
V
+
IN
R
2
R
2
7, 10
V
REF
V
O
A compensation scheme built into the
DG
cell
compensates for temperature and cancels out odd harmonic
distortion. The only distortion which remains is even
harmonics, and they exist only because of internal offset
voltages. The THD trim terminal provides a means for
nulling the internal offsets for low distortion operation.
The operational amplifier (which is internally
compensated) has the non−inverting input tied to V
REF
, and
the inverting input connected to the
DG
cell output as well
2.2mF 10kW
V
2
2, 15
4
1, 16
2.2mF
30kW
5, 12
8.2kW
8, 9
200pF
Figure 3. Typical Test Circuit
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SA571
INTRODUCTION
Much interest has been expressed in high performance
electronic gain control circuits. For non−critical
applications,
an
integrated
circuit
operational
transconductance amplifier can be used, but when
high−performance is required, one has to resort to complex
discrete circuitry with many expensive, well−matched
components. This paper describes an inexpensive integrated
circuit, the SA571 Compandor, which offers a pair of high
performance gain control circuits featuring low distortion
(<0.1%), high signal−to−noise ratio (90 dB), and wide
dynamic range (110 dB).
Circuit Background
requires a simple full−wave averaging rectifier with good
accuracy, since the rectifier accuracy determines the (input)
output level tracking accuracy. The gain cell determines the
distortion and noise characteristics, and the phone system
specifications here are very loose. These specs could have
been met with a simple Operational Transconductance
Multiplier, or OTA, but the gain of an OTA is proportional
to temperature and this is very undesirable. Therefore, a
linearized transconductance multiplier was designed which
is insensitive to temperature and offers low noise and low
distortion performance. These features make the circuit
useful in audio and data systems as well as in
telecommunications systems.
Basic Hook−up and Operation
The SA571 Compandor was originally designed to satisfy
the requirements of the telephone system. When several
telephone channels are multiplexed onto a common line, the
resulting signal−to−noise ratio is poor and companding is
used to allow a wider dynamic range to be passed through
the channel. Figure 4 graphically shows what a compandor
can do for the signal−to−noise ratio of a restricted dynamic
range channel. The input level range of +20 to −80 dB is
shown undergoing a 2−to−1 compression where a 2.0 dB
input level change is compressed into a 1.0 dB output level
change by the compressor. The original 100 dB of dynamic
range is thus compressed to a 50 dB range for transmission
through a restricted dynamic range channel. A
complementary expansion on the receiving end restores the
original signal levels and reduces the channel noise by as
much as 45 dB.
The significant circuits in a compressor or expander are
the rectifier and the gain control element. The phone system
COMPRESSION
EXPANSION
Figure 5 shows the block diagram of one half of the chip,
(there are two identical channels on the IC). The full−wave
averaging rectifier provides a gain control current, I
G
, for the
variable gain (DG) cell. The output of the
DG
cell is a current
which is fed to the summing node of the operational
amplifier. Resistors are provided to establish circuit gain and
set the output DC bias.
The circuit is intended for use in single power supply
systems, so the internal summing nodes must be biased at
some voltage above ground. An internal band gap voltage
reference provides a very stable, low noise 1.8 V reference
denoted V
REF
. The non−inverting input of the op amp is tied
to V
REF
, and the summing nodes of the rectifier and
DG
cell
(located at the right of R
1
and R
2
) have the same potential.
The THD trim pin is also at the V
REF
potential.
THD TRIM
OUTPUT
LEVEL
−20
0dB
8,9
R
3
G
IN
3,14
RECT
IN
R
2
20kW
R
1
R
3
INV
IN
6,11
5,12
INPUT
LEVEL
+20
0dB
20kW
DG
IG
R
4
30kW
V
REF
1.8V
V
CC
PIN 13
1,16
C
RECT
GND PIN 4
−
+
OUTPUT
7,10
−40
NOISE
−80
−40
2,15 10kW
−80
Figure 4. Restricted Dynamic Range Channel
Figure 5. Chip Block Diagram (1 of 2 Channels)
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