WAN PLL
IDT82V3280
NRND - Not Recommend for New Designs
FOR REPLACEMENT DEVICE USE IDT82V3280A
Version 7
April 15, 2015
6024 Silver Creek Valley Road, San Jose, CA 95138
Telephone: (800) 345-7015 • TWX: 910-338-2070 • FAX: (408) 284-2775
Printed in U.S.A.
© 2009 Integrated Device Technology, Inc.
DISCLAIMER
Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best pos-
sible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry
described herein is free from patent infringement or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent, patent rights or other
rights, of Integrated Device Technology, Inc.
LIFE SUPPORT POLICY
Integrated Device Technology's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is exe-
cuted between the manufacturer and an officer of IDT.
1. Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform, when properly used in
accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any components of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its
safety or effectiveness.
Table of Contents
NRND - Not Recommend for New Designs
FEATURES .............................................................................................................................................................................. 9
HIGHLIGHTS.................................................................................................................................................................................................... 9
MAIN FEATURES ............................................................................................................................................................................................ 9
OTHER FEATURES ......................................................................................................................................................................................... 9
APPLICATIONS....................................................................................................................................................................... 9
DESCRIPTION....................................................................................................................................................................... 10
FUNCTIONAL BLOCK DIAGRAM ........................................................................................................................................ 11
1 PIN ASSIGNMENT ........................................................................................................................................................... 12
2 PIN DESCRIPTION .......................................................................................................................................................... 13
3 FUNCTIONAL DESCRIPTION ......................................................................................................................................... 19
RESET ........................................................................................................................................................................................................... 19
MASTER CLOCK .......................................................................................................................................................................................... 19
INPUT CLOCKS & FRAME SYNC SIGNAL ................................................................................................................................................. 20
3.3.1 Input Clocks .................................................................................................................................................................................... 20
3.3.2 Frame SYNC Input Signals ............................................................................................................................................................ 20
3.4 INPUT CLOCK PRE-DIVIDER ...................................................................................................................................................................... 21
3.5 INPUT CLOCK QUALITY MONITORING ..................................................................................................................................................... 23
3.5.1 LOS Monitoring .............................................................................................................................................................................. 23
3.5.2 Activity Monitoring ......................................................................................................................................................................... 23
3.5.3 Frequency Monitoring ................................................................................................................................................................... 24
3.6 T0 / T4 DPLL INPUT CLOCK SELECTION .................................................................................................................................................. 25
3.6.1 External Fast Selection (T0 only) .................................................................................................................................................. 25
3.6.2 Forced Selection ............................................................................................................................................................................ 26
3.6.3 Automatic Selection ....................................................................................................................................................................... 26
3.7 SELECTED INPUT CLOCK MONITORING .................................................................................................................................................. 27
3.7.1 T0 / T4 DPLL Locking Detection ................................................................................................................................................... 27
3.7.1.1 Fast Loss .......................................................................................................................................................................... 27
3.7.1.2 Coarse Phase Loss .......................................................................................................................................................... 27
3.7.1.3 Fine Phase Loss ............................................................................................................................................................... 27
3.7.1.4 Hard Limit Exceeding ....................................................................................................................................................... 27
3.7.2 Locking Status ............................................................................................................................................................................... 27
3.7.3 Phase Lock Alarm (T0 only) .......................................................................................................................................................... 28
3.8 SELECTED INPUT CLOCK SWITCH ........................................................................................................................................................... 29
3.8.1 Input Clock Validity ........................................................................................................................................................................ 29
3.8.2 Selected Input Clock Switch ......................................................................................................................................................... 29
3.8.2.1 Revertive Switch ............................................................................................................................................................... 29
3.8.2.2 Non-Revertive Switch (T0 only) ........................................................................................................................................ 30
3.8.3 Selected / Qualified Input Clocks Indication ................................................................................................................................ 30
3.9 SELECTED INPUT CLOCK STATUS VS. DPLL OPERATING MODE ....................................................................................................... 31
3.9.1 T0 Selected Input Clock vs. DPLL Operating Mode .................................................................................................................... 31
3.9.2 T4 Selected Input Clock vs. DPLL Operating Mode .................................................................................................................... 33
3.10 T0 / T4 DPLL OPERATING MODE ............................................................................................................................................................... 34
3.10.1 T0 DPLL Operating Mode .............................................................................................................................................................. 34
3.10.1.1 Free-Run Mode ................................................................................................................................................................ 34
3.10.1.2 Pre-Locked Mode ............................................................................................................................................................. 34
3.10.1.3 Locked Mode .................................................................................................................................................................... 34
3.1
3.2
3.3
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April 15, 2015
IDT82V3280
WAN PLL
3.11
3.12
3.13
3.14
3.15
3.16
3.17
4.1
5.1
5.2
5.3
5.4
5.5
4 TYPICAL APPLICATION ................................................................................................................................................. 47
MASTER / SLAVE APPLICATION ............................................................................................................................................................... 47
EPROM MODE .............................................................................................................................................................................................. 49
MULTIPLEXED MODE .................................................................................................................................................................................. 50
INTEL MODE ................................................................................................................................................................................................. 52
MOTOROLA MODE ...................................................................................................................................................................................... 54
SERIAL MODE .............................................................................................................................................................................................. 56
3.10.1.3.1 Temp-Holdover Mode .................................................................................................................................... 34
3.10.1.4 Lost-Phase Mode ............................................................................................................................................................. 34
3.10.1.5 Holdover Mode ................................................................................................................................................................. 34
3.10.1.5.1 Automatic Instantaneous ............................................................................................................................... 35
3.10.1.5.2 Automatic Slow Averaged ............................................................................................................................. 35
3.10.1.5.3 Automatic Fast Averaged .............................................................................................................................. 35
3.10.1.5.4 Manual ........................................................................................................................................................... 35
3.10.1.5.5 Holdover Frequency Offset Read .................................................................................................................. 35
3.10.1.6 Pre-Locked2 Mode ........................................................................................................................................................... 35
3.10.2 T4 DPLL Operating Mode .............................................................................................................................................................. 35
3.10.2.1 Free-Run Mode ................................................................................................................................................................ 35
3.10.2.2 Locked Mode .................................................................................................................................................................... 35
3.10.2.3 Holdover Mode ................................................................................................................................................................. 35
T0 / T4 DPLL OUTPUT ................................................................................................................................................................................. 37
3.11.1 PFD Output Limit ............................................................................................................................................................................ 37
3.11.2 Frequency Offset Limit .................................................................................................................................................................. 37
3.11.3 PBO (T0 only) ................................................................................................................................................................................. 37
3.11.4 Phase Offset Selection (T0 only) .................................................................................................................................................. 37
3.11.5 Four Paths of T0 / T4 DPLL Outputs ............................................................................................................................................. 37
3.11.5.1 T0 Path ............................................................................................................................................................................. 37
3.11.5.2 T4 Path ............................................................................................................................................................................. 38
T0 / T4 APLL ................................................................................................................................................................................................. 39
OUTPUT CLOCKS & FRAME SYNC SIGNALS ........................................................................................................................................... 39
3.13.1 Output Clocks ................................................................................................................................................................................. 39
3.13.2 Frame SYNC Output Signals ......................................................................................................................................................... 42
MASTER / SLAVE CONFIGURATION ......................................................................................................................................................... 44
INTERRUPT SUMMARY ............................................................................................................................................................................... 45
T0 AND T4 SUMMARY ................................................................................................................................................................................. 45
POWER SUPPLY FILTERING TECHNIQUES ............................................................................................................................................. 46
5 MICROPROCESSOR INTERFACE .................................................................................................................................. 48
6 JTAG ................................................................................................................................................................................ 58
7 PROGRAMMING INFORMATION .................................................................................................................................... 59
7.1
7.2
REGISTER MAP ............................................................................................................................................................................................ 59
REGISTER DESCRIPTION ........................................................................................................................................................................... 65
7.2.1 Global Control Registers ............................................................................................................................................................... 65
7.2.2 Interrupt Registers ......................................................................................................................................................................... 74
7.2.3 Input Clock Frequency & Priority Configuration Registers ....................................................................................................... 79
7.2.4 Input Clock Quality Monitoring Configuration & Status Registers ......................................................................................... 102
7.2.5 T0 / T4 DPLL Input Clock Selection Registers ........................................................................................................................... 116
7.2.6 T0 / T4 DPLL State Machine Control Registers ......................................................................................................................... 120
7.2.7 T0 / T4 DPLL & APLL Configuration Registers .......................................................................................................................... 122
7.2.8 Output Configuration Registers .................................................................................................................................................. 136
7.2.9 PBO & Phase Offset Control Registers ...................................................................................................................................... 146
7.2.10 Synchronization Configuration Registers ................................................................................................................................. 148
JUNCTION TEMPERATURE ...................................................................................................................................................................... 149
8 THERMAL MANAGEMENT ........................................................................................................................................... 149
8.1
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IDT82V3280
WAN PLL
9 ELECTRICAL SPECIFICATIONS .................................................................................................................................. 151
9.1
9.2
9.3
8.2
8.3
8.4
EXAMPLE OF JUNCTION TEMPERATURE CALCULATION ................................................................................................................... 149
HEATSINK EVALUATION .......................................................................................................................................................................... 149
TQFP EPAD THERMAL RELEASE PATH ................................................................................................................................................. 150
ABSOLUTE MAXIMUM RATING ................................................................................................................................................................ 151
RECOMMENDED OPERATION CONDITIONS .......................................................................................................................................... 151
I/O SPECIFICATIONS ................................................................................................................................................................................. 152
9.3.1 AMI Input / Output Port ................................................................................................................................................................ 152
9.3.1.1 Structure ......................................................................................................................................................................... 152
9.3.1.2 I/O Level ......................................................................................................................................................................... 152
9.3.1.3 Over-Voltage Protection ................................................................................................................................................. 154
9.3.2 CMOS Input / Output Port ............................................................................................................................................................ 154
9.3.3 PECL / LVDS Input / Output Port ................................................................................................................................................ 155
9.3.3.1 PECL Input / Output Port ................................................................................................................................................ 155
9.3.3.2 LVDS Input / Output Port ................................................................................................................................................ 157
9.3.3.3 Single-Ended Input for Differential Input ........................................................................................................................ 158
JITTER & WANDER PERFORMANCE ....................................................................................................................................................... 159
OUTPUT WANDER GENERATION ............................................................................................................................................................ 162
INPUT / OUTPUT CLOCK TIMING ............................................................................................................................................................. 163
OUTPUT CLOCK TIMING ........................................................................................................................................................................... 164
PACKAGE DIMENSIONS.................................................................................................................................................... 169
ORDERING INFORMATION................................................................................................................................................ 172
9.4
9.5
9.6
9.7
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April 15, 2015
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